參數(shù)資料
型號(hào)： LTC2298IUP#PBF
廠(chǎng)商： Linear Technology
文件頁(yè)數(shù)： 4/28頁(yè)
文件大?。?/td> 0K
描述： IC ADC DUAL 14BIT 65MSPS 64QFN
標(biāo)準(zhǔn)包裝： 40
位數(shù)： 14
采樣率（每秒）： 65M
數(shù)據(jù)接口： 并聯(lián)
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 450mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 64-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 64-QFN（9x9）
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)單端，雙極; 2 個(gè)差分, 雙極
LTC2298/LTC2297/LTC2296
12
229876fa
MUX (Pin 21): Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together.
SHDNB (Pin 22): Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to VDD and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to VDD
and OEB to VDD results in sleep mode with the outputs at
high impedance.
OEB (Pin 23): Channel B Output Enable Pin. Refer to
SHDNB pin function.
DB0 – DB13 (Pins 24 to 30, 33 to 39): Channel B Digital
Outputs. DB13 is the MSB.
OGND (Pins 31, 50): Output Driver Ground.
OVDD (Pins 32, 49): Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
F ceramic chip capacitor.
OFB (Pin 40): Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA13 (Pins 41 to 48, 51 to 56): Channel A Digital
Outputs. DA13 is the MSB.
OFA (Pin 57): Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58): Channel A Output Enable Pin. Refer to
SHDNA pin function.
SHDNA (Pin 59): Channel A Shutdown Mode Selection
Pin. Connecting SHDNA to GND and OEA to GND results
in normal operation with the outputs enabled. Connecting
SHDNA to GND and OEA to VDD results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNA to VDD and OEA to GND results in nap mode with
the outputs at high impedance. Connecting SHDNA to VDD
and OEA to VDD results in sleep mode with the outputs at
high impedance.
MODE (Pin 60): Output Format and Clock Duty Cycle
Stabilizer Selection Pin. Note that MODE controls both
channels. Connecting MODE to GND selects offset binary
output format and turns the clock duty cycle stabilizer off.
1/3 VDD selects offset binary output format and turns the
clock duty cycle stabilizer on. 2/3 VDD selects 2’s comple-
ment output format and turns the clock duty cycle stabi-
lizer on. VDD selects 2’s complement output format and
turns the clock duty cycle stabilizer off.
VCMA (Pin 61): Channel A 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
F ceramic chip
capacitor. Do not connect to VCMB.
SENSEA (Pin 62): Channel A Reference Programming Pin.
Connecting SENSEA to VCMA selects the internal reference
and a
±0.5V input range. VDD selects the internal reference
and a
±1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEA selects an input
range of
±VSENSEA. ±1V is the largest valid input range.
GND (Exposed Pad) (Pin 65): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
UU
U
PI FU CTIO S
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