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參數資料
| 型號： | LTC2356IMSE-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 6/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 14BIT 3.5MSPS 10-MSOP |
| 標準包裝： | 50 |
| 位數： | 14 |
| 采樣率（每秒）： | 3.5M |
| 數據接口： | 串行，SPI? |
| 轉換器數目： | 1 |
| 功率耗散（最大）： | 18mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）裸露焊盤 |
| 供應商設備封裝： | 10-MSOP 裸露焊盤 |
| 包裝： | 管件 |
| 輸入數目和類型： | 2 個單端，雙極；1 個差分，雙極 |
| 產品目錄頁面： | 1349 (CN2011-ZH PDF) |
| 配用： | DC1082A-E-ND - BOARD SAR ADC LTC2356-14 |
LTC2356-12/LTC2356-14
14
2356fb
VREF BYPASS 0805 SIZE
VDD BYPASS 0805 SIZE
2356 F07
OPTIONAL INPUT FILTERING
FREQUENCY (Hz)
MAGNITUDE
(dB)
–60
–30
–20
2356 F06b
–70
–80
–120
–100
0
–10
–40
–50
–90
–110
0
371k
185k
556k
741k
APPLICATIONS INFORMATION
Board Layout and Bypassing
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2356-12/LTC2356-14, a printed
circuit board with ground plane is required. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track. If optimum phase match
between the inputs is desired, the length of the two input
wires should be kept matched.
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Block Diagram on the first page of this data sheet. For
optimum performance, a 10F surface mount Tantalum
capacitor with a 0.1F ceramic is recommended for the
VDD and VREF pins. Alternatively, 10F ceramic chip
capacitors such as Murata GRM219R60J106M may
be used. The capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
Figure7showstherecommendedsystemgroundconnec-
tions. All analog circuitry grounds should be terminated
at the LTC2356-12/LTC2356-14 GND (Pins 4, 5, 6 and
exposed pad). The ground return from the LTC2356-
12/LTC2356-14 (Pins 4, 5, 6 and exposed pad) to the
power supply should be low impedance for noise free
operation. In applications where the ADC data outputs
and control signals are connected to a continuously ac-
tive microprocessor bus, it is possible to get errors in the
conversion results. These errors are due to feedthrough
from the microprocessor to the successive approximation
comparator. The problem can be eliminated by forcing the
microprocessor into a Wait state during conversion or by
using three-state buffers to isolate the ADC data bus.
POWER-DOWN MODES
Upon power-up, the LTC2356-12/LTC2356-14 is initial-
ized to the active state and is ready for conversion. The
Nap and Sleep mode waveforms show the power-down
modes for the LTC2356-12/LTC2356-14. The SCK and
CONV inputs control the power-down modes (see Timing
Diagrams).TworisingedgesatCONV,withoutanyinterven-
ing rising edges at SCK, put the LTC2356-12/LTC2356-14
in Nap mode and the power consumption drops from
18mW to 4mW. The internal reference remains powered
in Nap mode. One or more rising edges at SCK wake up
the LTC2356-12/LTC2356-14 very quickly, and CONV
can start an accurate conversion within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC2356-12/LTC2356-14 in Sleep
mode and the power consumption drops from 18mW
to 13W. One or more rising edges at SCK wake up the
LTC2356-12/LTC2356-14 for operation. The internal refer-
ence (VREF ) takes 2ms to slew and settle with a 10F load.
Figure 7. Recommended Layout
Figure 6b. LTC2356-12 6MHz Sine Wave 4096 Point FFT Plot
with the LT1819 Driving the Inputs Differentially
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