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參數(shù)資料
| 型號： | LTC2362HTS8#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 500KSPS TSOT23-8 |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 500k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.2mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 薄型，TSOT-23-8 |
| 供應商設(shè)備封裝： | TSOT-23-8 |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 配用： | DC1190A-C-ND - BOARD SAR ADC LTC2362 |
LTC2360/LTC2361/LTC2362
5
236012fa
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 4)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When pins AIN and VREF are taken below GND or above VDD,
they will be clamped by internal diodes. These products can handle input
currents greater than 100mA below GND or above VDD without latch-up.
Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
fSCK = fSCK(MAX) unless otherwise specied.
Note 5: Integral linearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
SYMBOL
PARAMETER
CONDITIONS
LTC2360
LTC2361
LTC2362
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
fSMPL(MAX)
Maximum Sampling Frequency
(Notes 8, 9)
l 100
250
500
kHz
fSCK
Shift Clock Frequency
(Notes 8, 9)
l
10
25
50
MHz
tSCK
Shift Clock Period
l 100
40
20
ns
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV
l
10
4
2
μs
tACQ
Acquisition Time
l
2
1
0.5
μs
tCONV
Conversion Time
l
8
3
1.5
μs
t1
Minimum Positive CONV Pulse Width
(Note 8)
l
8
3
1.5
μs
t2
SCK
↑ Setup Time After CONV↓
(Note 8)
l
16
ns
t3
SDO Enabled Time After CONV
↓
(Notes 8, 9)
l
16
ns
t4
SDO Data Valid Access Time After SCK
↓ (Notes 8, 9, 10) l
888
ns
t5
SCK Low Time
(Note 11)
l 40%
40%
tSCK
t6
SCK High Time
(Note 11)
l 40%
40%
tSCK
t7
SDO Data Valid Hold Time After SCK
↓
(Notes 8, 9, 10)
l
444
ns
t8
SDO Into Hi-Z State Time After CONV
↑
(Notes 8, 9)
6
ns
Note 6: Linearity, offset and gain specications apply for a single-ended
AIN input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specied with
tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specications given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: The time required for the output to cross the VIH or VIL voltage.
Note 11: Guaranteed by design, not subject to test.
Note 12: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
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