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參數(shù)資料
| 型號： | LTC2364IMS-18#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT 250K 1CH 16MSOP |
| 產(chǎn)品培訓(xùn)模塊： | LTC2369- 18-/16-bit Pseudo-Differential SAR ADC Family Overview |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 4.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TFSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
| 配用： | DC1813A-H-ND - BOARD SAR ADC LTC2364-18 |
LTC2364-18
10
236418f
OVERVIEW
TheLTC2364-18isalownoise,lowpower,highspeed18-bit
successive approximation register (SAR) ADC. Operating
from a single 2.5V supply, the LTC2364-18 supports a
0V to VREF pseudo-differential unipolar input range with
VREF ranging from 2.5V to 5.1V, making it ideal for high
performance applications which require a wide dynamic
range. The LTC2364-18 achieves ±2.5LSB INL max, no
missing codes at 18 bits and 97dB SNR.
Fast 250ksps throughput with no cycle latency makes
the LTC2364-18 ideally suited for a wide variety of high
speed applications. An internal oscillator sets the con-
version time, easing external timing considerations. The
LTC2364-18 dissipates only 3.4mW at 250ksps, while an
auto power-down feature is provided to further reduce
power dissipation during inactive periods.
CONVERTER OPERATION
The LTC2364-18 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins to
sample the pseudo-differential analog input voltage. A ris-
ing edge on the CNV pin initiates a conversion. During the
conversionphase,the18-bitCDACissequencedthrougha
successiveapproximationalgorithm,effectivelycomparing
the sampled input with binary-weighted fractions of the
reference voltage (e.g. VREF/2, VREF/4 … VREF/262144)
using the differential comparator. At the end of conver-
sion, the CDAC output approximates the sampled analog
input. The ADC control logic then prepares the 18-bit
digital output code for serial transfer.
TRANSFER FUNCTION
The LTC2364-18 digitizes the full-scale voltage of REF
into 218 levels, resulting in an LSB size of 19V with
REF = 5V. The ideal transfer function is shown in Figure2.
The output data is in straight binary format.
APPLICATIONS INFORMATION
Figure 2. LTC2364-18 Transfer Function
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2364-18
ANALOG INPUT
TheanaloginputsoftheLTC2364-18arepseudo-differential
in order to reduce any unwanted signal that is common
to both inputs. The analog inputs can be modeled by the
equivalentcircuitshowninFigure3.Thediodesattheinput
provide ESD protection. In the acquisition phase, each
input sees approximately 45pF (CIN) from the sampling
CDAC in series with 40Ω (RON) from the on-resistance
of the sampling switch. The IN+ input draws a current
spike while charging the CIN capacitor during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
INPUT VOLTAGE (V)
0V
OUTPUT
CODE
236418 F02
111...111
111...110
111...101
111...100
000...001
000...000
000...010
000...011
1
LSB
UNIPOLAR
ZERO
FS – 1LSB
1LSB = FS/262144
RON
40
CIN
45pF
RON
40
REF
CIN
45pF
IN+
IN–
BIAS
VOLTAGE
236418 F03
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