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參數(shù)資料
| 型號(hào)： | LTC2391HLX-16#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16B SER/PAR 250K 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 250k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 125mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 配用： | DC1500A-C-ND - BOARD SAR ADC LTC2391-16 |
LTC2391-16
11
239116fa
APPLICATIONS INFORMATION
OVERVIEW
The LTC2391-16 is a low noise, high speed 16-bit suc-
cessive approximation register (SAR) ADC. Operating
from a single 5V supply, the LTC2391-16 supports a large
±4.096V fully differential input range, making it ideal
for high performance applications which require a wide
dynamic range. The LTC2391-16 achieves ±2LSB INL max,
no missing codes at 16 bits and 94dB SNR (typ).
The LTC2391-16 includes a precision internal reference with
a guaranteed 0.5% initial accuracy and a ±20ppm/°C (max)
temperature coefcient. Fast 250ksps throughput with no
cycle latency in both parallel and serial interface modes
makes the LTC2391-16 ideally suited for a wide variety
of high speed applications. An internal oscillator sets the
conversion time, easing external timing considerations.
The LTC2391-16 dissipates only 95mW at 250ksps, while
both nap and sleep power-down modes are provided to
further reduce power during inactive periods.
CONVERTER OPERATION
The LTC2391-16 operates in two phases. During the ac-
quisition phase, the charge redistribution capacitor D/A
converter (CDAC) is connected to the IN+ and IN– pins
to sample the differential analog input voltage. A falling
edge on the CNVST pin initiates a conversion. During the
conversion phase, the 16-bit CDAC is sequenced through
a successive approximation algorithm, effectively compar-
ing the sampled input with binary-weighted fractions of
the reference voltage (e.g., VREF/2, VREF/4 … VREF/65536)
using the differential comparator. At the end of conversion,
the CDAC output approximates the sampled analog input.
The ADC control logic then prepares the 16-bit digital
output code for parallel or serial transfer.
TRANSFER FUNCTION
The LTC2391-16 digitizes the full-scale voltage of 2 VREF
into 216 levels, resulting in an LSB size of 125μV when VREF
= 4.096V. The ideal transfer function for two’s complement
is shown in Figure 2. The OB/2C pin selects either offset
binary or two’s complement format.
ANALOG INPUT
The analog inputs of the LTC2391-16 are fully differential
in order to maximize the signal swing that can be digitized.
The analog inputs can be modeled by the equivalent circuit
shown in Figure 3. The diodes at the input provide ESD pro-
tection. The analog inputs should not exceed the supply or
go below ground. In the acquisition phase, each input sees
approximately 40pF (CIN)fromthesamplingCDACinseries
with 50Ω (RIN) from the on-resistance of the sampling
switch. Any unwanted signal that is common to both
inputs will be reduced by the common mode rejection of
the ADC. The inputs draw only one small current spike
while charging the CIN capacitors during acquisition.
During conversion, the analog inputs draw only a small
leakage current.
Figure 2. LTC2391-16 Two’s Complement Transfer Function
Figure 3. The Equivalent Circuit for the
Differential Analog Input of the LTC2391-16
INPUT VOLTAGE (V)
0V
OUTPUT
CODE
(T
WO’S
COMPLEMENT)
–1
LSB
239116 F02
011...111
011...110
000...001
000...000
100...000
100...001
111...110
1
LSB
BIPOLAR
ZERO
111...111
FSR/2 – 1LSB
–FSR/2
FSR = +FS – –FS
1LSB = FSR/65536
IN+
RIN
CIN
AVP
BIAS
VOLTAGE
IN–
RIN
239116 F03
CIN
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