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參數(shù)資料
| 型號： | LTC2402IMS |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-/2-Channel 24-Bit uPower No Latency ADC in MSOP-10 |
| 中文描述： | 2-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO10 |
| 封裝： | PLASTIC, MSOP-10 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 171K |
| 代理商： | LTC2402IMS |
6
LTC2401/LTC2402
APPLICATIOU
Output Data Format
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicat-
ing the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is LOW if the last conversion
was performed on CH0 and HIGH for CH1.
Bit 29 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero
code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
≤
V
IN
≤
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
W
U
U
Table 1. LTC2401/LTC2402 Status Bits
Bit 31
EOC
0
0
0
0
Bit 30
CH0/CH1
0/1
0/1
0/1
0/1
Bit 29
SIG
1
1
1/0
0
Bit 28
EXR
1
0
0
1
Input Range
V
IN
> V
REF
0 < V
IN
≤
V
REF
V
IN
= 0
+
/0
–
V
IN
< 0
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 1. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
MSB
EXT
SIG
CH0/CH1
1
2
3
4
5
27
28
32
BIT 0
BIT 27
BIT 4
LSB
24
BIT 28
BIT 29
BIT 30
SDO
SCK
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
24012 F01
Hi-Z
Figure 1. Output Data Timing
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