參數(shù)資料
型號(hào): LTC2404CG
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 4-/8-Channel 24-Bit uPower No Latency ADCs
中文描述: 4-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝: 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù): 29/36頁
文件大小: 351K
代理商: LTC2404CG
29
LTC2404/LTC2408
noise bandwidth of the system to 6Hz. The noise band-
width of the LTC2408 without any input bandwidth lim-
iting is approximately 150Hz. A roll-off at 1500Hz
eliminates all higher order images of the base bandwidth
of 6Hz. In the example shown, the optional bandwidth-
limit
ing filter has a –3dB point at 1450Hz. This filter can be
inserted after the multiplexer provided that higher source
impedance prior to the multiplexer does not reduce the
–3dB frequency, extending settling time, and resulting in
charge sharing between samples. The settling time of this
filter to 20+ bits of accuracy is less than 2ms. In the pres-
ence of external wideband noise, this filter reduces the
apparent noise by a factor of 5. Note that the noise band-
width for noise developed in the amplifier is 150Hz. In the
example shown, the gain of the amplifier is set to 40, the
point at which amplifier noise gain dominates the LTC2408
noise. Input voltage range as shown is then 0V to 125mV
DC. The recommended capacitor at C2 for a gain of 40
would be 560pF.
Interfacing the LTC2404/LTC2408 to the 68HC11
Microcontroller
The listing in Figure 28 is a simple assembler routine for
the 68HC11 microcontroller. It uses PORT D, configuring
it for SPI data transfer between the controller and the
LTC2408. The program shows how to select and enable a
MUX channel and retrieve conversion data. Figure 27 shows
the simple 4-wire SPI connection.
APPLICATIO
S I
FOR
ATIO
U
W
U
U
LTC2408
CLK
SCK
SD0
CSADC
CSMUX
D
IN
19
25
24
23
20
21
68HC11
24048 F27
SCK (PD4)
MISO (PD2)
SS (PD5)
MOSI (PD3)
Figure 27. Connecting the LTC2408 to a
68HC11 MCU Using the SPI Serial Interface
T
he code begins by declaring variables and allocating four
memory locations to store the 32-bit conversion result
and a fifth location to store the MUX channel address. This
is followed by initializing PORT D’s SPI configuration. The
program then enters the main sequence. It begins by
sending the MUX channel data. It then activates the
LTC2408’s serial interface by setting the SS output low,
sending a logic low to CSADC/CSMUX. This also activates
the selected MUX channel. It next waits in a loop for a logic
low on the data line, signifying end-of-conversion. After
the loop is satisfied, four SPI transfers are completed,
retrieving the conversion. The main sequence ends by
setting SS high. This places the LTC2408’s serial interface
in a high impedance state and initiates another conver-
sion. The program in Figure 30 modifies the MUX channel
selection routine in Figure 28’s listing for selection of 16
channels. Figure 29 shows the connections between the
LTC1391, LTC2408 and the 68HC11 controller.
**********************************************************
*
* This example program loads multiplexer channels selection data into *
* the LTC2408’s internal MUX and then transfers the LTC2408’s 32-bit *
* output conversion result to four consecutive 8-bit memory locations. *
*
**********************************************************
*
***************************************
* 68HC11 register definitions
***************************************
*
PORTD
EQU
$1008
Port D data register
*
“ - , - , SS* ,CSK ;MOSI,MISO,TxD ,RxD “
DDRD
EQU
$1009
Port D data direction register
SPCR
EQU
$1028
SPI control register
*
“SPIE,SPE ,DWOM,MSTR;SPOL,CPHA,SPR1,SPR0”
SPSR
EQU
$1029
SPI status register
*
“SPIF,WCOL, - ,MODF; - , - , - , - “
SPDR
EQU
$102A
SPI data register; Read-Buffer; Write-Shifter
*
* RAM variables to hold the LTC2408’s 32 conversion result
*
*
*
*
相關(guān)PDF資料
PDF描述
LTC2404IG 4-/8-Channel 24-Bit uPower No Latency ADCs
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LTC2404I 18-Bit Universal Bus Driver With 3-State Outputs 56-TSSOP -40 to 85
LTC2408 18-Bit Universal Bus Driver With 3-State Outputs 56-TVSOP -40 to 85
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