參數(shù)資料
型號： LTC2408IG
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 4-/8-Channel 24-Bit uPower No Latency ADCs
中文描述： 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28
封裝： 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù)： 5/36頁
文件大?。?/td> 351K
代理商： LTC2408IG
5
LTC2404/LTC2408
The
G
denotes specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25
°
C. (Note 3)
f
EOSC
t
HEO
t
LEO
t
CONV
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time
G
2.56
0.5
0.5
130.66
156.80
307.2
390
390
136
163.20
kHz
μ
s
μ
s
ms
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
G
G
F
O
= 0V
F
O
= V
CC
External Oscillator (Note 11)
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
(Note 10)
(Note 9)
(Note 9)
(Note 9)
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
(Note 9)
G
G
G
133.33
160
20480/f
EOSC
(in kHz)
19.2
f
EOSC
/8
f
ISCK
Internal SCK Frequency
D
ISCK
f
ESCK
t
LESCK
t
HESCK
t
DOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 32-Bit Data Output Time
45
55
2000
G
G
250
250
1.64
G
G
G
1.67
1.70
256/f
EOSC
(in kHz)
32/f
ESCK
(in kHz)
t
DOUT_ESCK
t
1
t
2
t
3
t
4
t
KQMAX
t
KQMIN
t
5
t
6
External SCK 32-Bit Data Output Time
CS
↓
to SDO Low Z
CS
↑
to SDO High Z
CS
↓
to SCK
↓
CS
↓
to SCK
↑
SCK
↓
to SDO Valid
SDO Hold After SCK
↓
SCK Set-Up Before CS
↓
SCK Hold After CS
↓
G
G
0
0
0
150
150
150
G
(Note 10)
(Note 9)
G
G
50
G
200
(Note 5)
G
15
50
G
G
50
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Note 1:
Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2:
All voltage values are with respect to GND.
Note 3:
V
CC
= 2.7 to 5.5V unless otherwise specified, source input
is 0
.
Note 4:
Internal Conversion Clock source with the F
O
pin tied
to GND or to V
CC
or to external conversion clock source with
f
EOSC
= 153600Hz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7:
F
O
= 0V (internal oscillator) or f
EOSC
= 153600Hz
±
2%
(external oscillator).
Note 8:
F
O
= V
CC
(internal oscillator) or f
EOSC
= 128000Hz
±
2%
(external oscillator).
Note 9:
The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is f
ESCK
and is expressed in kHz.
Note 10:
The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance C
LOAD
= 20pF.
Note 11:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12:
The converter uses the internal oscillator.
F
O
= 0V or F
O
= V
CC
.
Note 13:
The output noise includes the contribution of the internal
calibration operations.
Note 14:
For reference voltage values V
REF
> 2.5V the extended input
of –0.125 V
REF
to 1.125 V
REF
is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < V
REF
≤
0.267V + 0.89 V
CC
the input voltage range is –0.3V to 1.125 V
REF
.
For 0.267V + 0.89 V
CC
< V
REF
≤
V
CC
the input voltage range is –0.3V
to V
CC
+ 0.3V.
Note 15:
V
S
is the voltage applied to a channel input. V
D
is the voltage
applied to the MUX output.
TI I G CHARACTERISTICS
U
W
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