參數資料
型號： LTC2410IGN#TR
廠商： Linear Technology
文件頁數： 28/48頁
文件大?。?/td> 0K
描述： IC ADC 24BIT DIFF INP/REF 16SSOP
標準包裝： 2,500
位數： 24
采樣率（每秒）： 7.5
數據接口： MICROWIRE?，串行，SPI?
轉換器數目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 16-SSOP
包裝： 帶卷 (TR)
輸入數目和類型： 1 個差分，雙極
配用： DC575A-ND - BOARD DELTA SIGMA ADC LTC2410
LTC2410
34
APPLICATIO S I FOR ATIO
WU
U
Traditional high order delta-sigma modulators, while pro-
viding very good linearity and resolution, suffer from po-
tential instabilities at large input signal levels. The propri-
etary architecture used for the LTC2410 third order modu-
lator resolves this problem and guarantees a predictable
stable behavior at input signal levels of up to 150% of full
scale. In many industrial applications, it is not uncommon
to have to measure microvolt level signals superimposed
over volt level perturbations and LTC2410 is eminently
suited for such tasks. When the perturbation is differential,
the specification of interest is the normal mode rejection
for large input signal levels. With a reference voltage
VREF = 5V, the LTC2410 has a full-scale differential input
range of 5V peak-to-peak. Figures 43 and 44 show mea-
surement results for the LTC2410 normal mode rejection
ratio with a 7.5V peak-to-peak (150% of full scale) input
signal superimposed over the more traditional normal mode
rejection ratio results obtained with a 5V peak-to-peak (full
scale) input signal. In Figure 43, the LTC2410 uses the
internal oscillator with the notch set at 60Hz (FO = LOW)
and in Figure 44 it uses the internal oscillator with the
notch set at 50Hz (FO = HIGH). It is clear that the LTC2410
rejection performance is maintained with no compromises
in this extreme situation. When operating with large input
signal levels, the user must observe that such signals do
not violate the device absolute maximum ratings.
SYNCHRONIZATION OF MULTIPLE LTC2410s
Since the LTC2410’s absolute accuracy (total unadjusted
error) is 5ppm, applications utilizing multiple synchro-
nized ADCs are possible.
Figure 43. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (60Hz Notch)
Figure 44. Measured Input Normal Mode Rejection vs Input Frequency with Input Perturbation of 150% Full Scale (50Hz Notch)
INPUT FREQUENCY (Hz)
0
15
30
45
60
75
90
105 120 135 150 165 180 195 210 225 240
NORMAL
MODE
REJECTION
(dB)
2410 F43
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF – = GND
VINCM = 2.5V
FO = GND
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL
MODE
REJECTION
(dB)
2410 F44
0
–20
–40
–60
–80
–100
–120
VCC = 5V
REF+ = 5V
REF – = GND
VINCM = 2.5V
FO = 5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
12.5
25
37.5
50
62.5
75
87.5 100 112.5 125 137.5 150 162.5 175 187.5 200
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