參數資料
型號： LTC2412CGN#PBF
廠商： Linear Technology
文件頁數： 25/36頁
文件大?。?/td> 0K
描述： IC ADC 2CH DIFF-IN 24BIT 16SSOP
標準包裝： 100
位數： 24
采樣率（每秒）： 7.5
數據接口： MICROWIRE?，串行，SPI?
轉換器數目： 1
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應商設備封裝： 16-SSOP
包裝： 管件
輸入數目和類型： 1 個差分，雙極
產品目錄頁面： 1347 (CN2011-ZH PDF)
配用： DC746A-ND - BOARD DELTA SIGMA ADC LTC2412
LTC2412
31
2412f
APPLICATIO S I FOR ATIO
WU
U
input driving amplifier. This bandwidth includes the band
limiting effects of the ADC internal calibration and filtering.
The noise of the driving amplifier referred to the converter
input and including all these effects can be calculated as
N = ni √freqi. The total system noise (referred to the
LTC2412 input) can now be obtained by summing as
square root of sum of squares the three ADC input referred
noise sources: the LTC2412 internal noise (800nV), the
noise of the IN+ driving amplifier and the noise of the IN–
driving amplifier.
If the FO pin is driven by an external oscillator of frequency
fEOSC, Figure 32 can still be used for noise calculation if the
x-axis is scaled by fEOSC/153600. For large values of the
ratio fEOSC/153600, the Figure 32 plot accuracy begins to
decrease, but in the same time the LTC2412 noise floor
rises and the noise contribution of the driving amplifiers
lose significance.
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2412 significantly
simplifies antialiasing filter requirements.
The Sinc4 digital filter provides greater than 120dB normal
mode rejection at all frequencies except DC and integer
multiples of the modulator sampling frequency (fS). The
LTC2412’s autocalibration circuits further simplify the
antialiasing requirements by additional normal mode sig-
nal filtering both in the analog and digital domain. Inde-
pendent of the operating mode, fS = 256 fN = 2048
fOUTMAX where fN in the notch frequency and fOUTMAX is
the maximum output data rate. In the internal oscillator
mode with a 50Hz notch setting, fS = 12800Hz and with a
60Hz notch setting fS = 15360Hz. In the external oscillator
mode, fS = fEOSC/10.
The combined normal mode rejection performance is
shown in Figure 33 for the internal oscillator with 50Hz
notch setting (FO = HIGH) and in Figure 34 for the internal
oscillator with 60Hz notch setting (FO = LOW) and for the
external oscillator mode. The regions of low rejection
occurring at integer multiples of fS have a very narrow
bandwidth. Magnified details of the normal mode rejection
curves are shown in Figure 35 (rejection near DC) and
Figure 33. Input Normal Mode Rejection,
Internal Oscillator and 50Hz Notch
Figure 34. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Notch or External Oscillator
Figure 32. Input Referred Noise Equivalent Bandwidth
of an Input Connected White Noise Source
INPUT NOISE SOURCE SINGLE POLE
EQUIVALENT BANDWIDTH (Hz)
1
INPUT
REFERRED
NOISE
EQUIVALENT
BANDWIDTH
(Hz)
10
0.1
1
10
100
1k
10k
100k
1M
2412 F32
0.1
100
FO = HIGH
FO = LOW
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0fS 2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS10fS11fS12fS
INPUT
NORMAL
MODE
REJECTION
(dB)
2412 F33
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
FO = HIGH
FO = LOW OR
FO = EXTERNAL
OSCILLATOR,
fEOSC = 10 fS
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0fS
INPUT
NORMAL
MODE
REJECTION
(dB)
2412 F34
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
2fS 3fS 4fS 5fS 6fS 7fS 8fS 9fS 10fS
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