參數(shù)資料
型號(hào)： LTC2414
廠商： Linear Technology Corporation
英文描述： 2-Channel Differential Input 24-Bit No Latency DS ADC
中文描述： 2路差分輸入24位ADC的無(wú)延遲局副局長(zhǎng)
文件頁(yè)數(shù)： 24/36頁(yè)
文件大小： 409K
代理商： LTC2414
LTC2412
24
2412f
APPLICATIU
W
U
U
For a simple approximation, the source impedance R
S
driving an analog input pin (IN
+
, IN
–
, REF
+
or REF
–
) can be
considered to form, together with R
SW
and C
EQ
(see
Figure11), a first order passive network with a time
constant
τ
= (R
S
+ R
SW
) C
EQ
. The converter is able to
sample the input signal with better than 1ppm accuracy if
the sampling period is at least 14 times greater than the
input circuit time constant
τ
. The sampling process on the
four input analog pins is quasi-independent so each time
constant should be considered by itself and, under worst-
case circumstances, the errors may add.
When using the internal oscillator (F
O
= LOW or HIGH), the
LTC2412’s front-end switched-capacitor network is clocked
at 76800Hz corresponding to a 13
μ
s sampling period.
Thus, for settling errors of less than 1ppm, the driving
source impedance should be chosen such that
τ
≤
13
μ
s/14
= 920ns. When an external oscillator of frequency f
EOSC
is
used, the sampling period is 2/f
EOSC
and, for a settling
error of less than 1ppm,
τ
≤
0.14/f
EOSC
.
Input Current
If complete settling occurs on the input, conversion re-
sults will be unaffected by the dynamic input current. An
incomplete settling of the input signal sampling process
may result in gain and offset errors, but it will not degrade
the INL performance of the converter. Figure 11 shows the
mathematical expressions for the average bias currents
flowing through the IN
+
and IN
–
pins as a result of the
sampling charge transfers when integrated over a sub-
stantial time period (longer than 64 internal clock cycles).
The effect of this input dynamic current can be analyzed
using the test circuit of Figure 12. The C
PAR
capacitor
includes the LTC2412 pin capacitance (5pF typical) plus
the capacitance of the test fixture used to obtain the results
shown in Figures 13 and 14. A careful implementation can
bring the total input capacitance (C
IN
+ C
PAR
) closer to 5pF
thus achieving better performance than the one predicted
by Figures 13 and 14. For simplicity, two distinct situa-
tions can be considered.
For relatively small values of input capacitance (C
IN
<
0.01
μ
F), the voltage on the sampling capacitor settles
almost completely and relatively large values for the
source impedance result in only small errors. Such values
C
IN
2412 F12
V
INCM
+ 0.5V
IN
R
SOURCE
IN
+
LTC2412
C
PAR
20pF
C
IN
V
INCM
– 0.5V
IN
R
SOURCE
IN
–
C
PAR
Figure 12. An RC Network at IN
+
and IN
–
Figure 14. –FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
Figure 13. +FS Error vs R
SOURCE
at IN
+
or IN
–
(Small C
IN
)
R
SOURCE
(
)
1
10
100
1k
10k
100k
+
R
)
2412 F13
50
40
30
20
10
0
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= 5V
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
R
SOURCE
(
)
1
10
100
1k
10k
100k
–
R
)
2412 F14
0
–10
–20
–30
–40
–50
V
= 5V
REF
+
= 5V
REF
–
= GND
IN
+
= GND
IN
–
= 2.5V
F
O
= GND
T
A
= 25
°
C
C
IN
= 0.01
μ
F
C
IN
= 0.001
μ
F
C
IN
= 100pF
C
IN
= 0pF
for C
IN
will deteriorate the converter offset and gain
performance without significant benefits of signal filtering
and the user is advised to avoid them. Nevertheless, when
small values of C
IN
are unavoidably present as parasitics
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