Figure 29. INL vs Differential Input Voltage (V
參數(shù)資料
型號： LTC2415-1IGN
廠商： Linear Technology
文件頁數(shù)： 25/40頁
文件大?。?/td> 0K
描述： IC ADC 24BIT DIFFINPUT/REF16SSOP
標(biāo)準(zhǔn)包裝： 100
位數(shù)： 24
采樣率（每秒）： 13.75
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸入數(shù)目和類型： 1 個差分，雙極
LTC2415/LTC2415-1
31
sn2415 24151fs
APPLICATIO S I FOR ATIO
WU
U
Figure 29. INL vs Differential Input Voltage (VIN = IN+ – IN–) and Reference
Source Resistance (RSOURCE at REF+ and REF– for Large CREF Values (CREF ≥ 1F)
VINDIF/VREFDIF
–0.5 –0.4–0.3–0.2–0.1 0
0.1 0.2 0.3 0.4 0.5
INL
(ppm
OF
V
REF
)
15
12
9
6
3
0
–3
–6
–9
–12
–15
VCC = 5V
REF+ = 5V
REF– = GND
VINCM = 0.5 (IN
+ + IN–) = 2.5V
FO = GND
CREF = 10F
TA = 25°C
RSOURCE = 1000
RSOURCE = 500
RSOURCE = 100
2415 F29
tance is 1.43M
. When FO is driven by an external
oscillator with a frequency fEOSC (external conversion
clock operation), the typical differential reference resis-
tance is 0.20 1012/fEOSC and each ohm of source
resistance driving REF+ or REF– will result in
2.47 10–6 fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF+ and REF– pins and external capacitance CREF
connected to these pins are shown in Figures 25, 26, 27
and 28.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
When FO = LOW (internal oscillator and 60Hz notch), every
100
of source resistance driving REF+ or REF– translates
into about 1.34ppm additional INL error. For the LTC2415,
when FO = HIGH (internal oscillator and 50Hz notch), every
100
of source resistance driving REF+ or REF– translates
into about 1.1ppm additional INL error; and for the
LTC2415-1 operating with simultaneous 50Hz/60Hz re-
jection, every 100
of source resistance leads to an
additional 1.22ppm of additional INL error. When FO is
driven by an external oscillator with a frequency fEOSC,
every 100
of source resistance driving REF+ or REF–
translates into about 8.73 10–6 fEOSCppm additional INL
error. Figure 26 shows the typical INL error due to the
source resistance driving the REF+ or REF– pins when
large CREF values are used. The effect of the source
resistance on the two reference pins is additive with
respect to this INL error. In general, matching of source
impedance for the REF+ and REF– pins does not help the
gain or the INL error. The user is thus advised to minimize
the combined source impedance driving the REF+ and
REF– pins rather than to try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
0.5%. Such a specification can also be easily achieved by
an external clock. When relatively stable resistors
(50ppm/
°C) are used for the external source impedance
seen by REF+ and REF–, the expected drift of the dynamic
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
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