Figure 15. CS Capacitance vs tSAMPLE F" />
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    參數(shù)資料
    型號: LTC2415IGN
    廠商: Linear Technology
    文件頁數(shù): 18/40頁
    文件大?。?/td> 0K
    描述: IC A/D CONV 24BIT MICRPWR 16SSOP
    標準包裝: 100
    位數(shù): 24
    采樣率(每秒): 15
    數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
    轉(zhuǎn)換器數(shù)目: 2
    功率耗散(最大): 1mW
    電壓電源: 單電源
    工作溫度: -40°C ~ 85°C
    安裝類型: 表面貼裝
    封裝/外殼: 16-SSOP(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 16-SSOP
    包裝: 管件
    輸入數(shù)目和類型: 1 個差分,雙極
    LTC2415/LTC2415-1
    25
    sn2415 24151fs
    APPLICATIO S I FOR ATIO
    WU
    U
    Figure 15. CS Capacitance vs tSAMPLE
    Figure 16. CS Capacitance vs Output Rate
    Figure 17. CS Capacitance vs Supply Current
    CAPACITANCE ON CS (pF)
    1
    5
    6
    7
    1000
    10000
    2415 F15
    4
    3
    10
    100
    100000
    2
    1
    0
    t SAMPLE
    (SEC)
    VCC = 5V
    VCC = 3V
    CAPACITANCE ON CS (pF)
    0
    SAMPLE
    RATE
    (Hz)
    3
    4
    5
    1000
    100000
    2415 F16
    2
    1
    0
    10
    100
    10000
    6
    7
    8
    VCC = 5V
    VCC = 3V
    CAPACITANCE ON CS (pF)
    1
    0
    SUPPLY
    CURRENT
    (
    A
    RMS
    )
    50
    100
    150
    200
    250
    300
    10
    100
    1000
    10000
    2415 F17
    100000
    VCC = 5V
    VCC = 3V
    66.6ms and the conversion time of the LTC2413 is 146ms,
    while the LTC2415-1 is 73ms. In systems where the SDO
    pin is monitored for the end-of-conversion signal (SDO
    goes low once the conversion is complete) these two
    devices can be interchanged. In cases where SDO is not
    monitored, a wait state is inserted between conversions,
    the duration of this wait state must be greater than 66.6ms
    for the LTC2415, greater than 133ms for the LTC2410,
    greater than 146ms for the LTC2413 and greater than
    73ms for the LTC2415-1.
    PRESERVING THE CONVERTER ACCURACY
    The LTC2415/LTC2415-1 are designed to reduce as much
    as possible conversion result sensitivity to device
    decoupling, PCB layout, antialiasing circuits, line fre-
    quency perturbations and so on. Nevertheless, in order to
    preserve the extreme accuracy capability of this part,
    some simple precautions are desirable.
    Digital Signal Levels
    The LTC2415/LTC2415-1 digital interface is easy to use.
    Its digital inputs (FO, CS and SCK in External SCK mode of
    operation) accept standard TTL/CMOS logic levels and the
    internal hysteresis receivers can tolerate edge rates as slow
    as 100
    s. However, some considerations are required to
    take advantage of the exceptional accuracy and low supply
    current of this converter.
    The digital output signals (SDO and SCK in Internal SCK
    mode of operation) are less of a concern because they are
    not generally active during conversion.
    While a digital input signal is in the range 0.5V to
    (VCC – 0.5V), the CMOS input receiver draws additional
    current from the power supply. It should be noted that,
    when any one of the digital input signals (FO, CS and SCK
    in External SCK mode of operation) is within this range, the
    LTC2415/LTC2415-1 power supply current may increase
    even if the signal in question is at a valid logic level. For
    micropower operation, it is recommended to drive all
    digital input signals to full CMOS levels [VIL < 0.4V and
    VOH > (VCC – 0.4V)].
    During the conversion period, the undershoot and/or
    overshoot of a fast digital signal connected to the LTC2415/
    Timing Compatibility with the LTC2410/LTC2413
    All timing modes described above are identical with re-
    spect to the LTC2410/LTC2413 and LTC2415/LTC2415-1,
    with one exception. The conversion time of the LTC2410
    is 133ms while the conversion time of the LTC2415 is
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