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參數(shù)資料
| 型號： | LTC2420IS8 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 20-Bit uPower No Latency ADC in SO-8 |
| 中文描述： | 1-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | 0.150 INCH, PLASTIC, SO-8 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 186K |
| 代理商： | LTC2420IS8 |
6
LTC2420
APPLICATIU
W
U
U
CS
SCK
SDO
CONVERSION
SLEEP
8
8
8
8 (OPTIONAL)
EOC = 1
EOC = 1
LAST 8 BITS ALWAYS 1
EOC = 0
DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
2420 F01
CONVERSION
Figure 1. LTC2420 Compatible Timing with the LTC2400
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0
≤
V
IN
≤
V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2420 Status Bits
Bit 23
EOC
0
0
0
0
Bit 22
DMY
0
0
0
0
Bit 21
SIG
1
1
1/0
0
Bit 20
EXR
1
0
0
1
Input Range
V
IN
> V
REF
0 < V
IN
≤
V
REF
V
IN
= 0
+
/0
–
V
IN
< 0
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 2. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 23 (EOC) can be captured on the first rising
edge of SCK. Bit 22 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 23rd SCK and may be latched on
the rising edge of the 24th SCK pulse. On the falling edge
of the 24th SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 23) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the V
IN
pin is maintained within
the –0.3V to (V
CC
+ 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from –0.125 V
REF
to 1.125 V
REF
.
For input voltages
greater than 1.125 V
REF
, the conversion result is clamped
to the value corresponding to 1.125 V
REF
. For input
voltages below –0.125 V
REF
, the conversion result is
clamped to the value corresponding to –0.125 V
REF
.
Operation at Higher Data Output Rates
The LTC2420 typically operates with an internal oscillator
of 153.6kHz. This corresponds to a notch frequency of
60Hz and an output rate of 7.5 samples/second. The
internal oscillator is enabled if the F
O
pin is logic LOW
(logic HIGH for a 50Hz notch). It is possible to drive the F
O
pin with an external oscillator for higher data output rates.
As shown in Figure 3, an external clock of 2.048MHz
applied to the F
O
pin results in a notch frequency of 800Hz
with a data output rate of 100 samples/second.
Figure 4 shows the total unadjusted error (Offset Error +
Full-Scale Error + INL + DNL) as a function of the output
data rate with a 5V reference. The relationship between the
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