參數(shù)資料
型號(hào)： LTC2431CMS#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 13/40頁(yè)
文件大小： 0K
描述： IC ADC 20BIT DIFFINPUT/REF10MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 20
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 1mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 1 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 1348 (CN2011-ZH PDF)
配用： DC586A-ND - BOARD DELTA SIGMA ADC LTC2431
LTC2430/LTC2431
20
24301f
internal pull-up is not available to restore SCK to a logic
HIGH state. This will cause the device to exit the internal
serial clock mode on the next falling edge of CS. This can
be avoided by adding an external 10k pull-up resistor to
the SCK pin or by never pulling CS HIGH when SCK is LOW.
Whenever SCK is LOW, the LTC2430/LTC2431’s internal
pull-up at pin SCK is disabled. Normally, SCK is not exter-
nally driven if the device is in the internal SCK timing mode.
However, certain applications may require an external
driver on SCK. If this driver goes Hi-Z after outputting a LOW
signal, the LTC2430/LTC2431’s internal pull-up remains
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK timing
mode. By adding an external 10k pull-up resistor to SCK,
this pin goes HIGH once the external driver goes Hi-Z. On
the next CS falling edge, the device will remain in the in-
ternal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the conver-
sion status. If the device is in the sleep state (EOC = 0),
SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
Figure 10. Internal Serial Clock, CS = 0 Continuous Operation
APPLICATIO S I FOR ATIO
WU
UU
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
BIT 19
BIT 18
BIT 20
BIT 21
BIT 22
EOC
BIT 23
DATA OUTPUT
CONVERSION
2431 F10
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
2-WIRE I/O
LTC2430/
LTC2431
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
VCC
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