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參數(shù)資料
| 型號： | LTC2431IMS#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/40頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 20BIT DIFFINPUT/REF10MSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個差分，雙極 |
| 配用： | DC586A-ND - BOARD DELTA SIGMA ADC LTC2431 |
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LTC2430/LTC2431
26
24301f
into about 0.11ppm additional INL error. When FO = HIGH
(internal oscillator and 50Hz notch), every 100
of source
resistance driving REF+ or REF– translates into about
0.092ppm additional INL error. When FO is driven by an
external oscillator with a frequency fEOSC, every 100 of
source resistance driving REF+ or REF– translates into
about 0.73 10–6 fEOSCppm additional INL error. Fig-
ure 19 shows the typical INL error due to the source
resistance driving the REF+ or REF– pins when large CREF
values are used. The effect of the source resistance on the
two reference pins is additive with respect to this INL error.
In general, matching of source impedance for the REF+
APPLICATIO S I FOR ATIO
WU
UU
and REF– pins does not help the gain or the INL error. The
user is thus advised to minimize the combined source
impedance driving the REF+ and REF– pins rather than to
try to match it.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typical better than
1%. Such a specification can also be easily achieved by an
external clock. When relatively stable resistors (50ppm/
°C)
are used for the external source impedance seen by REF+
and REF–, the expected drift of the dynamic current gain
error will be insignificant (about 1% of its value over the
entire temperature and voltage range). Even for the most
stringent applications, a one-time calibration operation
may be sufficient.
In addition to the reference sampling charge, the reference
pins ESD protection diodes have a temperature dependent
leakage current. This leakage current, nominally 1nA
(
±10nA max), results in a small gain error. A 100 source
resistance will create a 0.05
V typical and 0.5V maxi-
mum full-scale error.
Figure 18a. +FS Error vs RSOURCE at REF
+ or REF– (Large CREF)
Figure 18b. – FS Error vs RSOURCE at REF+ or REF– (Large CREF)
RSOURCE ()
–50
–60
+
FS
ERROR
(ppm)
–30
–10
0
–40
–20
200
400
600
800
2431 F18a
1000
100
0
300
500
700
900
CREF = 1F, 10F
CREF = 0.1F
CREF = 0.01F
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 3.75V
VIN– = 1.25V
FO = GND
TA = 25°C
RSOURCE ()
10
0
–
FS
ERROR
(ppm)
30
50
60
20
40
200
400
600
800
2431 F18b
1000
100
0
300
500
700
900
CREF = 1F, 10F
CREF = 0.1F
CREF = 0.01F
VCC = 5V
VREF+ = 5V
VREF– = GND
VIN+ = 1.25V
VIN– = 3.75V
FO = GND
TA = 25°C
Figure 19. INL vs Differential Input Voltage (VIN = IN+ – IN–)
and Reference Source Resistance (RSOURCE at REF+ and REF–)
for Large CREF Values (CREF ≥ 1F)
VINDIF/VREFDIF
–0.5
INL
(ppm
OF
V
REF
)
3
9
15
0.3
2431 F19
–3
–9
0
6
12
–6
–12
–15
–0.3
–0.4
–0.1
–0.2
0.1 0.2
0.4
0
0.5
RSOURCE = 1k
RSOURCE = 10k
RSOURCE = 5k
VCC = 5V
VREF+ = 5V
VREF– = GND
VINCM = 0.5(VIN
+ + V
IN
–) = 2.5V
FO = GND
CREF = 10F
TA = 25°C
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