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參數(shù)資料
| 型號： | LTC2436-1 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 2-Channel Differential Input 16-Bit No Latency DS ADC |
| 中文描述： | 2路差分輸入16位ADC的無延遲局副局長 |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 292K |
| 代理商： | LTC2436-1 |
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LTC2436-1
10
24361f
Bit 18 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 17 (second output bit) is the selected channel indicator.
The bit is LOW for channel 0 and HIGH for channel 1
selected.
Bit 16 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW.
Bit 15 (fourth output bit) is the most significant bit (MSB)
of the result. This bit in conjunction with Bit 16 also
provides the underrange or overrange indication. If both
Bit 16 and Bit 15 are HIGH, the differential input voltage is
above +FS. If both Bit 16 and Bit 15 are LOW, the
differential input voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2436-1 Status Bits
Bit 18
EOC
0
0
0
0
Bit 17
CH0/CH1
0 or 1
0 or 1
0 or 1
0 or 1
Bit 16 Bit 15
SIG
1
1
0
0
Input Range
V
IN
≥
0.5 V
REF
0V
≤
V
IN
< 0.5 V
REF
–0.5 V
REF
≤
V
IN
< 0V
V
IN
< –0.5 V
REF
MSB
1
0
1
0
Bits 15-0 are the 16-Bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 3. Whenever CS is HIGH, SDO
remains high impedance and any externally generated
SCK clock pulses are ignored by the internal data out shift
register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external micro-
controller. Bit 18 (EOC) can be captured on the first rising
edge of SCK. Bit 17 is shifted out of the device on the first
falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 18th SCK and may be latched on
the rising edge of the 19th SCK pulse. On the falling edge
of the 19th SCK pulse, SDO goes HIGH indicating the
initiation of a new conversion cycle. This bit serves as EOC
(Bit 18) for the next conversion cycle. Table 2 summarizes
the output data format.
In order to remain compatible with some SPI
microcontrollers, more than 19 SCK clock pulses may be
applied. As long as these clock edges are complete before
the conversion ends, they will not effect the serial data.
However, switching SCK during a conversion may gener-
ate ground currents in the device leading to extra offset
and noise error sources.
As long as the voltage on the analog input pins is main-
tained within the –0.3V to (V
CC
+ 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage V
IN
from –FS = –0.5 V
REF
to
+FS = 0.5 V
REF
. For differential input voltages greater than
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
Figure 3. Output Data Timing
MSB
SIG
CH0/CH1
1
2
3
4
5
17
18
19
BIT 0
BIT 14
BIT 1
LSB
16
BIT 15
BIT 16
BIT 17
SDO
SCK
CS
EOC
BIT 18
SLEEP
DATA OUTPUT
CONVERSION
24361 F03
Hi-Z
APPLICATIOU
W
U
U
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