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參數(shù)資料
| 型號： | LTC2436-1CGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-Channel Differential Input 16-Bit No Latency DS ADC |
| 中文描述： | 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 292K |
| 代理商： | LTC2436-1CGN |
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LTC2436-1
14
24361f
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC=1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is
shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for abort-
ing an invalid conversion cycle or synchronizing the start
of a conversion.
Figure 7. External Serial Clock, Reduced Data Output Length
SDO
SCK
(EXTERNAL)
CS
DATA
OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC (OPTIONAL)
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
24361 F07
MSB
SIG
CH0/CH1
BIT 4
BIT 14
BIT 5
BIT 15
BIT 16
BIT 17
EOC
BIT 18
BIT 0
EOC
Hi-Z
TEST EOC
V
CC
F
O
REF
+
SCK
CH1
+
CH1
–
SDO
GND
CS
1
14
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
CH0
+
CH0
–
4
5
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1
μ
F
2.7V TO 5.5V
LTC2436-1
3-WIRE
SPI INTERFACE
REF
–
SLEEP
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
APPLICATIOU
W
U
U
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