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參數(shù)資料
| 型號： | LTC2439-1IGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 16CH MCRPWR 28SSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 配用： | DC790A-ND - BOARD DELTA SIGMA ADC LTC2439-1 |
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LTC2439-1
5
24391fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
●
2.56
2000
kHz
tHEO
External Oscillator High Period
●
0.25
390
s
tLEO
External Oscillator Low Period
●
0.25
390
s
tCONV
Conversion Time
FO = 0V
●
143.8
146.7
149.6
ms
External Oscillator (Note 10)
●
20510/fEOSC (in kHz)
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
17.5
kHz
External Oscillator (Notes 9, 10)
fEOSC/8
kHz
DISCK
Internal SCK Duty Cycle
(Note 9)
●
45
55
%
fESCK
External SCK Frequency Range
(Note 8)
●
2000
kHz
tLESCK
External SCK Low Period
(Note 8)
●
250
ns
tHESCK
External SCK High Period
(Note 8)
●
250
ns
tDOUT_ISCK
Internal SCK 19-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
●
1.06
1.09
1.11
ms
External Oscillator (Notes 9, 10)
●
152/fEOSC (in kHz)
ms
tDOUT_ESCK
External SCK 19-Bit Data Output Time
(Note 7)
●
19/fESCK (in kHz)
ms
t1
CS
↓ to SDO Low
●
0
200
ns
t2
CS
↑ to SDO High Z
●
0
200
ns
t3
CS
↓ to SCK ↓
(Note 9)
●
0
200
ns
t4
CS
↓ to SCK ↑
(Note 8)
●
50
ns
tKQMAX
SCK
↓ to SDO Valid
●
220
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
●
15
ns
t5
SCK Set-Up Before CS
↓
●
50
ns
t6
SCK Hold After CS
↓
●
50
ns
t7
SDI Setup Before SCK
↑
(Note 5)
●
100
ns
t8
SDI Hold After SCK
↑
(Note 5)
●
100
ns
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
U
W
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN
+ + IN–)/2, IN+ and IN– are defined as the selected positive
and negative input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a precise analog input voltage. Maximum specifications are limited by
the LSB step size (VREF/216) and the single shot measurement. Typical
specifications are measured from the center of the quantization band.
Note 7: FO = GND (internal oscillator) or fEOSC = 139800Hz ±2%
(external oscillator).
Note 8: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 9: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 12: 1
V RMS noise is independent of VREF. Since the noise
performance is limited by the quantization, lowering VREF improves the
effective resolution.
Note 13: Guaranteed by design and test correlation.
Note 14: The low sleep mode current is valid only when CS is high.
Note 15: These parameters are guaranteed by design over the full
supply and temperature range. Automated testing procedures are
limited by the LSB Step Size (VREF/216).
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