參數(shù)資料
型號(hào)： LTC2440
廠商： Linear Technology Corporation
英文描述： 2-Channel Differential Input 24-Bit No Latency DS ADC
中文描述： 2路差分輸入24位ADC的無延遲局副局長(zhǎng)
文件頁數(shù)： 21/36頁
文件大?。?/td> 409K
代理商： LTC2440
LTC2412
21
2412f
APPLICATIU
W
U
U
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
CC
exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating the
conversion has finished and the device has entered the
data output state. The data output cycle begins on the
first rising edge of SCK and ends after the 32nd rising
edge. Data is shifted out the SDO pin on each falling edge
of SCK. The internally generated serial clock is output
to the SCK pin. This signal may be used to shift the
conversion result into external circuitry. EOC can be
latched on the first rising edge of SCK and the last bit of
the conversion result can be latched on the 32nd rising
edge of SCK. After the 32nd rising edge, SDO goes HIGH
(EOC = 1) indicating a new conversion is in progress. SCK
remains HIGH during the conversion.
Figure 9. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>t
EOCtest
MSB
SIG
CH0/CH1
BIT 8
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DATA
OUTPUT
CONVERSION
CONVERSION
SLEEP
2412 F09
<t
EOCtest
V
CC
10k
TEST EOC
(OPTIONAL)
TEST EOC
= 50Hz REJECTION
= EXTERNAL OSCILLATOR
= 60Hz REJECTION
V
CC
V
CC
F
O
REF
+
SCK
CH1
+
CH1
–
SDO
GND
CS
1
14
2
3
13
6
7
12
8, 9, 10, 15, 16
11
REFERENCE
VOLTAGE
0.1V TO V
CC
CH0
+
CH0
–
4
5
ANALOG INPUT RANGE
–0.5V
REF
TO 0.5V
REF
1
μ
F
2.7V TO 5.5V
LTC2412
3-WIRE
SPI INTERFACE
REF
–
SLEEP
SLEEP
相關(guān)PDF資料
PDF描述
LTC2411-1 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85
LTC2412 16-Bit Universal Bus Driver With 3-State Outputs 48-SSOP -40 to 85
LTC2412CGN 16-Bit Universal Bus Driver With 3-State Outputs 48-TVSOP -40 to 85
LTC2414 2-Channel Differential Input 24-Bit No Latency DS ADC
LTC2418 Replaced by SN74ALVCH16374 : 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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LTC2440CGN#PBF 制造商:Linear Technology 功能描述:24BIT ADC DELTA SIG HS 16SSOP 制造商:Linear Technology 功能描述:24BIT ADC, DELTA SIG, HS, 16SSOP
LTC2440CGN#TR 功能描述:IC CONV A/D 24-BIT DIFF 16-SSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極
LTC2440CGN#TRPBF 功能描述:IC ADC DIFFER 24-BIT HS 16-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個(gè)單端，單極
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