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參數(shù)資料
| 型號： | LTC2442IG#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 22/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 4CH 36-SSOP |
| 標準包裝： | 37 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 50mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 36-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC979A-ND - BOARD DELTA SIGMA ADC LTC2442 |
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LTC2442
29
2442fa
For more information www.linear.com/LTC2442
Details of the Conversion and Autozero Process
The LTC2442 performs automatic offset cancellation for
each conversion. This is accomplished by taking the av-
erage of two “half-conversions” with the inputs applied in
opposite polarity. Figure 21 shows a conversion on CH0 to
CH1 differential at OSR of 32768, in 1x mode. This chan-
nel is selected by sending the appropriate configuration
word to the LTC2442 through the SPI interface. On the
13th falling clock edge, the CH0 input is applied to +INA
through the multiplexer and CH1 is connected to +INB.
The outputs of the amplifiers slew during the remainder
of the data I/O state and the conversion begins on the
32nd falling clock edge. Halfway through the conversion
(approximately 73ms later) the multiplexer switches the
CH0 input to +INB and the CH1 input to +INA. The digital
filter subtracts the two half-conversions, which removes
the offset of the amplifiers and converter.
At the end of a conversion, the multiplexer assumes that
the next conversion will be on the same channel and
switches back to the opposite polarity on the channel just
converted. This gives extra settling time when converting
on one channel continuously. If a different channel is
programmed, the multiplexer will switch again on the 13th
falling clock edge.
The amplifiers take approximately 50s to settle for a
full-scale input voltage. This does not affect accuracy in
either 2x mode or 1x mode for OSR values between 256
to 32768. However, the amplifier settling time will cause
a gain error in 1x mode for OSR values between 64 to
256. This is because the mid-conversion slew time is a
significant portion of the total conversion time. Figure 22
shows the details of a conversion in 1x mode, OSR128,
with a full-scale input voltage applied (VIN = 2.5V, VCM =
2.5V). The previously selected channel had both inputs
grounded. On the 13th falling clock edge, the amplifiers
begin slewing and have reached the correct voltage before
theconversionbegins.Midwaythroughtheconversion,the
multiplexerreversestheinputs.Figure23showsoperation
in 2x mode. After the first half-conversion is done, the
multiplexer reverses. Waiting 50s before beginning the
next half-conversion allows the amplifiers to settle fully.
2x mode is recommended for OSR values between 64 and
128becausetheamplifiershavetimetosettlebetweenhalf
conversions. If only the 1x data rate is required, ignore
every other sample.
Figure 21. Amplifier Outputs and CS, SCK, BUSY During a
Conversion on CH0-1, OSR32768. VINDIFF = 2.5V, VCM = 2.5V
applications inForMation
Figure 22. Details of Conversion in 1x Mode,
OSR128 (OUTA and OUTB Superimposed)
Figure 23. Details of Conversion in 2x Mode,
OSR128 (OUTA and OUTB Superimposed)
200ms/DIV
OUTB
2V/DIV
5V/DIV
OUTA
BUSY
SCK
CS
2442 F021
200s/DIV
OUTB
1V/DIV
5V/DIV
BUSY
SCK
CS
2442 F022
200s/DIV
OUTB
1V/DIV
5V/DIV
BUSY
SCK
CS
2442 F023
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