參數(shù)資料
型號: LTC2449C
廠商: Linear Technology Corporation
英文描述: 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution
中文描述: 24位ADC的高速8-/16-Channel可選速度/分辨率
文件頁數(shù): 23/28頁
文件大?。?/td> 270K
代理商: LTC2449C
LTC2444/LTC2445/
LTC2448/LTC2449
23
sn2444589 2444589fs
clock applied to F
O
. Combining a large OSR with a reduced
sample rate leads to notch frequencies f
N
near DC while
maintaining simple antialiasing requirements. A 100kHz
clock applied to F
O
results in a NULL at 0.6Hz plus all
harmonics up to 20kHz, see Figure 13. This is useful in
applications requiring digitalization of the DC component
of a noisy input signal and eliminates the need of placing
a 0.6Hz filter in front of the ADC.
An external oscillator operating from 100kHz to 20MHz
can be implemented using the LTC1799 (resistor set
SOT-23 oscillator), see Figure 16. By floating pin 4 (DIV)
of the LTC1799, the output oscillator frequency is:
f
MHz
k
R
OSC
SET
=
10
10
10
The normal mode rejection characteristic shown in
Figure 13 is achieved by applying the output of the LTC1799
(with R
SET
= 100k) to the F
O
pin on the LTC2444/LTC2445/
LTC2448/LTC2449 with SDI tied HIGH (OSR = 32768).
Figure 13. LTC2444/LTC2445/LTC2448/LTC2449 Normal
Mode Rejection (External Oscillator at 90kHz)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–40
–20
0
8
2440 F14
–60
–80
2
4
6
10
–100
–120
–140
N
Figure 12. LTC2444/LTC2445/LTC2448/LTC2449
Normal Mode Rejection (Internal Oscillator)
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0
–60
–40
0
1440 F13
–80
–100
1000000
2000000
–120
1.8MHz
–140
–20
N
REJECTION > 120dB
If F
O
is grounded, f
S
is set by the on-chip oscillator at
1.8MHz
±
5% (over supply and temperature variations). At
an OSR of 32,768, the first NULL is at f
N
= 55Hz and the no
latency output rate is f
N
/8 = 6.9Hz. At the maximum OSR,
the noise performance of the device is 280nV
RMS
(LTC2444/
LTC2448) and 200nV
RMS
(LTC2445/LTC2449) with better
than 80dB rejection of 50Hz
±
2% and 60Hz
±
2%. Since the
OSR is large (32,768) the wide band rejection is extremely
large and the antialiasing requirements are simple. The
first multiple of f
S
occurs at 55Hz 32,768 = 1.8MHz, see
Figure 12.
The first NULL becomes f
N
= 7.04kHz with an OSR of 256
(an output rate of 880Hz) and F
O
grounded. While the
NULL has shifted, the sample rate remains constant. As a
result of constant modulator sampling rate, the linearity,
offset and full-scale performance remains unchanged as
does the first multiple of f
S
.
The sample rate f
S
and NULL f
N
, may also be adjusted by
driving the F
O
pin with an external oscillator. The sample
rate is f
S
= f
EOSC
/5, where f
EOSC
is the frequency of the
APPLICATIOU
W
U
U
相關(guān)PDF資料
PDF描述
LTC2449CUHF 24-Bit High Speed 8-/16-Channel ADCs with Selectable Speed/Resolution
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