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參數(shù)資料
| 型號： | LTC2449CUHF#TR |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT HI SPEED 38QFN |
| 標準包裝： | 2,500 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 8k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 40mW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-QFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 配用： | DC742A-ND - BOARD DELTA SIGMA ADC LTC2449 |
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LTC2444/LTC2445/
LTC2448/LTC2449
5
2444589fb
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DISCK
Internal SCK Duty Cycle
(Note 9)
●
45
55
%
fESCK
External SCK Frequency Range
(Note 8)
●
20
MHz
tLESCK
External SCK Low Period
(Note 8)
●
25
ns
tHESCK
(Note 8)
●
25
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
●
41.6
35.3
30.9
s
External Oscillator (Notes 9, 10)
●
320/fEOSC
s
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 8)
●
32/fESCK
s
t1
CS
↓ to SDO Low Z
(Note 12)
●
025
ns
t2
CS
↑ to SDO High Z
(Note 12)
●
025
ns
3
CS
↓ to SCK ↓
(Note 9)
5
s
t4
CS
↓ to SCK ↑
(Notes 8, 12)
●
25
ns
tKQMAX
SCK
↓ to SDO Valid
●
25
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
●
15
ns
t5
SCK Set-Up Before CS
↓
●
50
ns
t6
SCK Hold After CS
↓
●
50
ns
t7
SDI Set-Up Before SCK
↑
(Note 5)
●
10
ns
t8
SDI Hold After SCK
↑
(Note 5)
●
10
ns
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
W
U
GND (Pins 1, 4, 5, 6, 31, 32, 33): Ground. Multiple
ground pins internally connected for optimum ground
current flow and VCC decoupling. Connect each one of
these pins to a common ground plane through a low
impedance connection. All 7 pins must be connected to
ground for proper operation.
BUSY (Pin 2): Conversion in Progress Indicator. This pin
is HIGH while the conversion is in progress and goes LOW
indicating the conversion is complete and data is ready. It
remains LOW during the sleep and data output states. At
the conclusion of the data output state, it goes HIGH
indicating a new conversion has begun.
EXT (Pin 3): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting/
inputting data. If EXT is tied low, the device is in the
external SCK mode and data is shifted out of the device
under the control of a user applied serial clock. If EXT is
tied high, the internal serial clock mode is selected. The
device generates its own SCK signal and outputs this on
the SCK pin. A framing signal BUSY (Pin 2) goes low
indicating data is being output.
COM (Pin 7): The common negative input (IN–) for all
single ended multiplexer configurations. The voltage on
CH0-CH15 and COM pins can have any value between
UU
U
PI FU CTIO S
Note 1: Absolute Maximum Ratings are those values beyond which the life
of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5V to 5.5V unless otherwise specified.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN
+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: FO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in Hz.
Note 11: The converter uses the internal oscillator. FO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1
s (typ) to the
conversion time.
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