參數(shù)資料
型號(hào)： LTC2450CDC-1#TRPBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT DELTA SIG 6-DFN
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 30
數(shù)據(jù)接口： 串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.05mW
電壓電源： 單電源
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 6-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 6-DFN-EP（2x2）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 1 個(gè)單端，單極
配用： DC1067A-B-ND - BOARD DELTA SIGMA ADC LTC2450-1
DC1067A-A-ND - BOARD DELTA SIGMA ADC LTC2450
LTC2450-1
7
24501fc
CONVERTER OPERATION
Converter Operation Cycle
The LTC2450-1 is a low power, delta-sigma analog-to-
digital converter with a simple 3-wire interface (see
Figure 1). Its operation is composed of three successive
states: CONVERT, SLEEP and DATA OUTPUT. The operat-
ing cycle begins with the CONVERT state, is followed
by the SLEEP state, and ends with the DATA OUTPUT
state (see Figure 2). The 3-wire interface consists of
serial data output (SDO), serial clock input (SCK), and the
active low chip select input (CS).
The CONVERT state duration is determined by the LTC2450-
1 conversion time (nominally 16.6 milliseconds). Once
started, this operation can not be aborted except by a low
power supply condition (VCC < 2.1V) which generates an
internal power-on reset signal.
After the completion of a conversion, the LTC2450-1
enters the SLEEP state and remains there until both the
chip select and clock inputs are low (CS = SCK = LOW).
Following this condition the ADC transitions into the DATA
OUTPUT state.
Figure 2. LTC2450-1 State Transition Diagram
APPLICATIONS INFORMATION
While in the SLEEP state, whenever the chip select in-
put is pulled high (CS = HIGH), the LTC2450-1’s power
supply current is reduced to less than 500nA. When the
chip select input is pulled low (CS = LOW), and SCK is
maintained at a HIGH logic level, the LTC2450-1 will return
to a normal power consumption level. During the SLEEP
state, the result of the last conversion is held indenitely
in a static register.
Upon entering the DATA OUTPUT state, SDO outputs the
most signicant bit (D15) of the conversion result. During
this state, the ADC shifts the conversion result serially
through the SDO output pin under the control of the SCK
input pin. There is no latency in generating this data and
the result corresponds to the last completed conversion.
A new bit of data appears at the SDO pin following each
falling edge detected at the SCK input pin. The user can
reliably latch this data on every rising edge of the external
serial clock signal driving the SCK pin (see Figure 3).
The DATA OUTPUT state concludes in one of two different
ways. First, the DATA OUTPUT state operation is completed
once all 16 data bits have been shifted out and the clock
then goes low. This corresponds to the 16th falling edge
of SCK. Second, the DATA OUTPUT state can be aborted
at any time by a LOW-to-HIGH transition on the CS input.
Following either one of these two actions, the LTC2450-1
will enter the CONVERT state and initiate a new conver-
sion cycle.
Power-Up Sequence
When the power supply voltage VCC applied to the con-
verter is below approximately 2.1V, the ADC performs a
power-on reset. This feature guarantees the integrity of
the conversion result.
When VCC rises above this critical threshold, the converter
generates an internal power-on reset (POR) signal for
approximately 0.5ms. The POR signal clears all internal
registers. Following the POR signal, the LTC2450-1 starts
a conversion cycle and follows the succession of states
described in Figure 2. The rst conversion result fol-
lowing POR is accurate within the specications of the
device if the power supply voltage VCC is restored within
the operating range (2.7V to 5.5V) before the end of the
POR time interval.
DATA OUTPUT
SLEEP
CONVERT
POWER-ON RESET
YES
24501 F02
16TH FALLING
EDGE OF SCK
OR
CS = HIGH?
SCK = LOW
AND
CS = LOW?
NO
YES
NO
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