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參數(shù)資料
| 型號： | LTC2450IDCTRPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Easy-to-Use, Ultra-Tiny 16-Bit ADC |
| 中文描述： | 易于使用，超微型16位ADC |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 628K |
| 代理商： | LTC2450IDCTRPBF |
LTC2450
2450fa
Examples of Aborting Cycle using
CS
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450 is in the
data output state, a
CS
rising edge clears the remaining data
bits from memory, aborts the output cycle and triggers a
new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the
CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
conversion operation can be triggered by pulling
CS
low
and then high. When
CS
is pulled low (
CS
= LOW), SDO
will output the most significant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and
CS
is subsequently pulled high
(
CS
= HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
applications inForMation
D
15
D
14
D
13
D
12
D
2
D
1
D
0
SD0
clk
1
clk
2
clk
3
DATA OUTPUT
clk
4
clk
15
clk
15
clk
16
SCK
CONVERT
CONVERT
SLEEP
LOW I
CC
2450 F08
CS
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
D
15
D
14
D
13
D
12
D
2
D
1
D
0
clk
1
clk
2
clk
3
clk
4
clk1
4
clk
15
clk
16
SCK
SD0
CONVERT
CONVERT
SLEEP
LOW I
CC
DATA OUTPUT
2450 F07
CS
Figure 7. Idle-Low (CPOL = 0) Clock.
CS
Triggers a New Conversion
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