TIMING CHARACTERISTICS The l denotes the specic" />
參數(shù)資料
型號： LTC2482IDD#PBF
廠商： Linear Technology
文件頁數(shù)： 28/32頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 10-DFN
標準包裝： 121
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 480µW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤
供應商設備封裝： 10-DFN（3x3）
包裝： 管件
輸入數(shù)目和類型： 1 個差分，雙極
產(chǎn)品目錄頁面： 1348 (CN2011-ZH PDF)
配用： DC941A-ND - BOARD DELTA SIGMA ADC LTC2482
LTC2482
5
2482fc
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
(Note 15)
l
10
4000
kHz
tHEO
External Oscillator High Period
l
0.125
100
μs
tLEO
External Oscillator Low Period
l
0.125
100
μs
tCONV_1
Conversion Time
Simultaneous 50Hz/60Hz
External Oscillator
l
144.1
146.9
41036/fEOSC (in kHz)
149.9
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
38.4
fEOSC/8
kHz
DISCK
Internal SCK Duty Cycle
(Note 10)
l
45
55
%
fESCK
External SCK Frequency Range
(Note 10)
l
4000
kHz
tLESCK
External SCK Low Period
(Note 10)
l
125
ns
tHESCK
External SCK High Period
(Note 10)
l
125
ns
tDOUT_ISCK
Internal SCK 24-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
l
0.61
0.625
192/fEOSC (in kHz)
0.64
ms
tDOUT_ESCK External SCK 24-Bit Data Output Time
(Note 10)
l
24/fESCK (in kHz)
ms
t1
CS↓ to SDO Low
l
0
200
ns
t2
CS
↑ to SDO Hi-Z
l
0
200
ns
t3
CS↓ to SCK
(Note 10)
l
0
200
ns
t4
CS↓ to SCK≠
(Note 10)
l
50
ns
tKQMAX
SCK
↓ to SDO Valid
l
200
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
l
15
ns
t5
SCK Set-Up Before CS
↓
l
50
ns
t6
SCK Hold After CS
↓
l
50
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specied:
VREFCM = VREF/2, FS = 0.5VREF
VIN = IN+ – IN–, VIN(CM) = (IN+ + IN–)/2
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specied.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: fEOSC = 256kHz ±2% (external oscillator).
Note 8: fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz rejection (internal oscillator) or
fEOSC = 280kHz ±2% (external oscillator).
Note 10: The SCK can be congured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as digital input and the
driving clock is fESCK. In internal SCK mode, the SCK pin is used as digital
output and the output clock signal during the data output is fISCK.
Note 11: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
Note 15: Refer to Applications Information section for performance vs
data rate graphs.
Note 16: For VCC < 3V, VIH is 2.5V for pin fO.
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