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| 型號(hào)： | LTC2484IDD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 121 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC939A-ND - BOARD DELTA SIGMA ADC LTC2484 |
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LTC2484
30
2484fd
APPLICATIONS INFORMATION
VREF translates into about 2.18 10–6 fEOSCppm addi-
tional INL error. Figure 19 shows the typical INL error due
to the source resistance driving the VREF pin when large
CREF values are used. The user is advised to minimize the
source impedance driving the VREF pin.
entire temperature and voltage range). Even for the most
stringent applications a one-time calibration operation
may be sufcient.
In addition to the reference sampling charge, the refer-
ence pins ESD protection diodes have a temperature
dependent leakage current. This leakage current, nominally
1nA (±10nA max), results in a small gain error. A 100Ω
source resistance will create a 0.05μV typical and 0.5μV
maximum full-scale error.
Output Data Rate
When using its internal oscillator, the LTC2484 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz, 6.25sps with a notch frequency of 50Hz and
6.8sps with the 50Hz/60Hz rejection mode. The actual
output data rate will depend upon the length of the sleep
and data output phases which are controlled by the user
and which can be made insignicantly short. When oper-
ated with an external conversion clock (fO connected to
an external oscillator), the LTC2484 output data rate can
be increased as desired. The duration of the conversion
phase is 41036/fEOSC. If fEOSC = 307.2kHz, the converter
behaves as if the internal oscillator is used and the notch
is set at 60Hz.
An increase in fEOSC over the nominal 307.2kHz will trans-
late into a proportional increase in the maximum output
data rate. The increase in output rate is nevertheless
accompanied by three potential effects, which must be
carefully considered.
First, a change in fEOSC will result in a proportional change
in the internal notch position and in a reduction of the
converter differential mode rejection at the power line
frequency. In many applications, the subsequent per-
formance degradation can be substantially reduced by
relying upon the LTC2484’s exceptional common mode
rejection and by carefully eliminating common mode to
differential mode conversion sources in the input circuit.
The user should avoid single-ended input lters and should
maintain a very high degree of matching and symmetry
in the circuits driving the IN+ and IN– pins.
Second, the increase in clock frequency will increase
proportionally the amount of sampling charge transferred
Figure 19. INL vs Differential Input Voltage and
Reference Source Resistance for CREF > 1μF
VIN/VREF (V)
–0.5
INL
(ppm
OF
V
REF
)
2
6
10
0.3
2484 F19
–2
–6
0
4
8
–4
–8
–10
–0.3
–0.1
0.1
0.5
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
CREF = 10μF
R = 1k
R = 100Ω
R = 500Ω
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (VREFCM – VINCM) and a 5V reference,
each Ohm of reference source resistance introduces an
extra (VREFCM – VINCM)/(VREF REQ) full-scale gain error,
which is 0.074ppm when using internal oscillator and 60Hz
mode. When using internal oscillator and 50Hz/60Hz mode,
the extra full-scale gain error is 0.067ppm. When using
internal oscillator and 50Hz mode, the extra gain error is
0.061ppm. If an external clock is used, the corresponding
extra gain error is 0.24 10–6 fEOSCppm.
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capacitors
and upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typically better than 0.5%. Such
a specication can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/°C) are
used for the external source impedance seen by VREF+
and GND, the expected drift of the dynamic current gain
error will be insignicant (about 1% of its value over the
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