參數(shù)資料
型號(hào)： LTC2486
廠商： Linear Technology Corporation
英文描述： 16-Bit 2-/4-Channel ツヒ ADC with PGA and Easy Drive Input Current Cancellation
中文描述： 16位2-/4-ChannelツヒADC，帶PGA和簡(jiǎn)易輸入電流驅(qū)動(dòng)取消
文件頁數(shù)： 5/36頁
文件大?。?/td> 596K
代理商： LTC2486
LTC2486
5
2486f
SYMBOL
f
EOSC
t
HEO
t
LEO
t
CONV_1
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
CONDITIONS
(Note 16)
MIN
10
0.125
0.125
157.2
131
144.1
TYP
MAX
4000
50
50
163.5
136.3
149.9
UNITS
kHz
●
●
μs
μs
ms
ms
ms
ms
ms
ms
ms
ms
kHz
kHz
%
kHz
ns
ns
ms
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
●
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
50Hz Mode
60Hz Mode
Simultaneous 50/60Hz Mode
External Oscillator
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
(Notes 10, 17)
(Notes 10, 11, 15)
(Notes 10, 11, 15)
(Notes 10, 11, 15)
Internal Oscillator (Notes 10, 17)
External Oscillator (Notes 10, 11, 15)
(Notes 10, 11, 15)
●
●
●
160.3
133.6
146.9
41036/f
EOSC
(in kHz)
80.3
66.9
73.6
20556/f
EOSC
(in kHz)
38.4
f
EOSC
/8
t
CONV_2
Conversion Time for 2x Speed Mode
●
●
●
78.7
65.6
72.2
81.9
68.2
75.1
f
ISCK
Internal SCK Frequency
D
ISCK
f
ESCK
t
LESCK
t
HESCK
t
DOUT_ISCK
Internal SCK Duty Cycle
External SCK Frequency Range
External SCK Low Period
External SCK High Period
Internal SCK 24-Bit Data Output Time
●
45
55
4000
●
●
125
125
0.61
●
●
0.625
192/f
EOSC
(in kHz)
24/f
ESCK
(in kHz)
0.64
t
DOUT_ESCK
t
1
t
2
t
3
t
4
t
KQMAX
t
KQMIN
t
5
t
7
t
8
External SCK 24-Bit Data Output Time
C
S
↓
to SDO Low
C
S
↑
to SDO High Z
C
S
↓
to SCK
↓
C
S
↓
to SCK
↑
SCK
↓
to SDO Valid
SDO Hold After SCK
↓
SCK Set-Up Before
C
S
↓
SDI Setup Before SCK
↑
SDI Hold After SCK
↑
●
0
0
0
200
200
200
●
Internal SCK Mode
External SCK Mode
●
●
50
●
200
(Note 5)
●
15
50
100
100
●
(Note 5)
(Note 5)
●
●
DIGITAL INPUTS AND DIGITAL OUTPUTS
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
The
●
denotes the specifications which apply over the
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2:
All voltage values are with respect to GND.
Note 3:
Unless otherwise specified:
V
CC
= 2.7V to 5.5V
V
REFCM
= V
REF
/2, F
S
= 0.5V
REF
/Gain
V
IN
= IN
+
– IN
–
, V
IN(CM)
= (IN
+
– IN
–
)/2,
where IN
+
and IN
–
are the selected input channels.
Note 4:
Use internal conversion clock or external conversion clock source
with f
EOSC
= 307.2kHz unless other wise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
50Hz mode (internal oscillator) or f
EOSC
= 256kHz ±2% (external
oscillator).
Note 8:
60Hz mode (internal oscillator) or f
EOSC
= 307.2kHz ±2% (external
oscillator).
Note 9:
Simultaneous 50Hz/60Hz mode (internal oscillator) or f
EOSC
=
280kHz ±2% (external oscillator).
Note 10:
The SCK can be configured in external SCK mode or internal SCK
mode. In external SCK mode, the SCK pin is used as a digital input and the
driving clock is f
ESCK
. In the internal SCK mode, the SCK pin is used as a
digital output and the output clock signal during the data output is f
ISCK
.
Note 11:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 12:
The converter uses its internal oscillator.
Note 13:
The output noise includes the contribution of the internal
calibration operations.
Note 14:
Guaranteed by design and test correlation.
Note 15:
The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is f
ESCK
and is expressed in Hz.
Note 16:
Refer to Applications Information section for performance vs
data rate graphs.
Note 17:
The converter in internal SCK mode of operation such that the
SCK pin is used as a digital output.
相關(guān)PDF資料
PDF描述
LTC2486CDE 16-Bit 2-/4-Channel ツヒ ADC with PGA and Easy Drive Input Current Cancellation
LTC2486IDE 16-Bit 2-/4-Channel ツヒ ADC with PGA and Easy Drive Input Current Cancellation
LTC2487 16-Bit 2-/4-Channel ADC with PGA, Easy Drive and I2C Interface
LTC2487CDEPBF 16-Bit 2-/4-Channel ADC with PGA, Easy Drive and I2C Interface
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