參數(shù)資料
型號(hào)： LTC2487CDETRPBF
廠商： Linear Technology Corporation
英文描述： 16-Bit 2-/4-Channel ADC with PGA, Easy Drive and I2C Interface
中文描述： 16位2-/4-Channel型ADC PGA巡回賽，輕松驅(qū)動(dòng)和I2C接口
文件頁(yè)數(shù)： 5/32頁(yè)
文件大小： 612K
代理商： LTC2487CDETRPBF
LTC2487
2487fa
power requireMenTs
range, otherwise specifications are at T
A
= 25°C. (Note 3)
SYMBOL
PARAMETER
V
CC
Supply Voltage
I
CC
Supply Current
The
●
denotes the specifications which apply over the full operating temperature
CONDITIONS
MIN
2.7
TYP
MAX
5.5
275
300
2
UNITS
●
V
Conversion Current (Note 11)
Temperature Measurement (Note 11)
Sleep Mode (Note 11)
●
●
●
160
200
1
μA
μA
μA
SYMBOL
f
EOSC
t
HEO
t
LEO
t
CONV_1
PARAMETER
External Oscillator Frequency Range
External Oscillator High Period
External Oscillator Low Period
Conversion Time for 1x Speed Mode
CONDITIONS
(Note 16)
MIN
10
0.125
0.125
157.2
131
144.1
TYP
MAX
4000
50
50
163.5
136.3
149.9
UNITS
kHz
●
●
μs
μs
ms
ms
ms
ms
ms
ms
ms
ms
●
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
●
●
●
160.3
133.6
146.9
41036/f
EOSC
(in kHz)
80.3
66.9
73.6
20556/f
EOSC
(in kHz)
t
CONV_2
Conversion Time for 2x Speed Mode
●
●
●
78.7
65.6
72.2
81.9
68.2
75.1
DigiTal inpuTs anD DigiTal ouTpuTs
full operating temperature range, otherwise specifications are at T
A
= 25°C. (Note 3)
The
●
denotes the specifications which apply over the
SYMBOL
f
SCL
t
HD(STA)
t
LOW
t
HIGH
t
SU(STA)
t
HD(DAT)
t
SU(DAT)
t
r
t
f
t
SU(STO)
PARAMETER
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Pin
High Period of the SCL Pin
Set-Up Time for a Repeated Start Condition
Data Hold Time
Data Set-Up Time
Rise Time for SDA Signals
Fall Time for SDA Signals
Set-Up Time for Stop Condition
CONDITIONS
MIN
0
0.6
1.3
0.6
0.6
0
100
TYP
MAX
400
UNITS
kHz
●
●
μs
μs
μs
μs
μs
ns
ns
ns
μs
●
●
●
●
0.9
●
(Note 14)
(Note 14)
●
20 + 0.1C
B
20 + 0.1C
B
0.6
300
300
●
●
i
2
c TiMing characTerisTics
temperature range, otherwise specifications are at T
A
= 25°C. (Note 3, 15)
The
●
denotes the specifications which apply over the full operating
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to GND.
Note 3:
Unless otherwise specified: V
CC
= 2.7V to 5.5V
V
REFCM
= V
REF
/2, F
S
= 0.5V
REF
/Gain
V
IN
= IN
+
– IN
–
, V
IN(CM)
= (IN
+
– IN
–
)/2,
where IN
+
and IN
–
are the selected input channels.
Note 4:
Use internal conversion clock or external conversion clock source
with f
EOSC
= 307.2kHz unless otherwise specified.
Note 5:
Guaranteed by design, not subject to test.
Note 6:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7:
50Hz mode (internal oscillator) or f
EOSC
= 256kHz ±2% (external oscillator).
Note 8:
60Hz mode (internal oscillator) or f
EOSC
= 307.2kHz ±2% (external oscillator).
Note 9:
Simultaneous 50Hz/60Hz mode (internal oscillator) or f
EOSC
=
280kHz ±2% (external oscillator).
Note 10:
The external oscillator is connected to the F
O
pin. The external
oscillator frequency, f
EOSC
, is expressed in kHz.
Note 11:
The converter uses its internal oscillator.
Note 12:
The output noise includes the contribution of the internal
calibration operations.
Note 13:
Guaranteed by design and test correlation.
Note 14:
C
B
= capacitance of one bus line in pF (10pF ≤ C
B
≤ 400pF).
Note 15:
All values refer to V
IH(MIN)
and V
IL(MAX)
levels.
Note 16:
Refer to Applications Information section for Performance vs
Data Rate graphs.
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