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參數(shù)資料
| 型號(hào)： | LTC2489 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-Bit 2-/4-Channel ADC with Easy Drive Input Current Cancellation and I2C Interface |
| 中文描述： | 16位2-/4-Channel ADC，具有易于驅(qū)動(dòng)的輸入電流取消和I2C接口 |
| 文件頁數(shù)： | 19/24頁 |
| 文件大?。?/td> | 341K |
| 代理商： | LTC2489 |
LTC2489
19
2489f
The SINC
4
digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (f
S
). The modulator
sampling frequency is f
S
= 15,360Hz while operating with
its internal oscillator and f
S
= f
EOSC
/20 when operating with
an external oscillator of frequency f
EOSC
.
When using the internal oscillator, the LTC2489 is designed
to reject line frequencies. As shown in Figure 15, rejection
nulls occur at multiples of frequency f
N
, where f
N
= 55Hz
for simultaneous 50Hz/60Hz rejection. Multiples of the
modulator sampling rate (f
S
= f
N
256) only reject noise
to 15dB (see Figure 16); if noise sources are present at
these frequencies antialiasing will reduce their effects.
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figure 17.
Measured values of normal mode rejection are shown
superimposed over the theoretical values.
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels. The
proprietary architecture used for the LTC2489 third order
modulator resolves this problem and guarantees stability
with input signals 150% of full scale. In many industrial
applications, it is not uncommon to have microvolt level
signals superimposed over unwanted error sources with
several volts if peak-to-peak noise. Figure 18 shows mea-
surement results for the rejection of a 7.5V peak-to-peak
noise source (150% of full scale) applied to the LTC2489.
This curve shows that the rejection performance is main-
tained even in extremely noisy environments.
Output Data Rate
When using its internal oscillator, the LTC2489 produces
up to 7.5 samples per second (sps) with a notch frequency
of 60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
APPLICATIONS INFORMATION
INPUT SIGNAL FREQUENCY (Hz)
I
2489 F15
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
f
N
0
2f
N
3f
N
4f
N
5f
N
6f
N
7f
N
8f
N
f
N
= f
EOSC/5120
INPUT SIGNAL FREQUENCY (Hz)
250f
N
252f
N
254f
N
256f
N
258f
N
260f
N
262f
N
I
2489 F16
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
f
N
= f
EOSC/5120
Figure 16. Input Normal Mode Rejection at f
S
= 256 f
N
Figure 15. Input Normal Mode Rejection at DC
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