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參數(shù)資料
| 型號： | LTC2493IDETRPBF |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 24-Bit 2-/4-Channel ADC with Easy Drive Input Current Cancellation and I2C Interface |
| 中文描述： | 24位2-/4-Channel ADC，具有易于驅(qū)動(dòng)的輸入電流取消和I2C接口 |
| 文件頁數(shù)： | 17/32頁 |
| 文件大?。?/td> | 588K |
| 代理商： | LTC2493IDETRPBF |
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LTC2493
2493fa
The first word (SGL, ODD, A2, A1, A0) is used to select the
input channel. The second word of data (IM, FA, FB, SPD)
is used to select the frequency rejection, speed mode (1x,
2x), and temperature measurement.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN
+
= CH0, IN
–
=
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled). The first
conversion automatically begins at power-up using this
default configuration. Once the conversion is complete,
up to two words may be written into the device.
The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits are 000 or 100, the following data
is ignored (don’t care) and the previously selected input
channel remains valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
The first input bit (SGL) following the 101 sequence de-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent chan-
nels can be selected to form a differential input. For SGL
= 1, one of 4 channels is selected as the positive input.
The negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
Once the first word is written into the device, a second
word may be input in order to select a configuration mode.
The first bit of the second word is the enable bit for the
conversion configuration (EN2). If this bit is set to 0, then
the next conversion is performed using the previously
selected converter configuration.
Figure 3a. Timing Diagram for Reading from the LTC2493
applicaTions inForMaTion
SLEEP
DATA OUTPUT
ACK BY
LTC2493
ACK BY
MASTER
SUB LSBs
START BY
MASTER
NAK BY
MASTER
LSB
R
MSB
SIG
D31
7
…
…
8
9
1
2
9
1
2
3
4
5
6
7
8
9
1
7-BIT
ADDRESS
2493 F03a
SCL
SDA
SLEEP
DATA INPUT
ACK BY
LTC2493
ACK BY
LTC2493
ACK BY
LTC2493
(OPTIONAL 2ND BYTE)
START BY
MASTER
SGL
ODD
W
0
1
SCL
SDA
EN
A2
A1
A0
7
…
8
9
1
2
9
1
2
3
4
5
6
7
8
2
3
4
5
6
7
8
9
1
7-BIT ADDRESS
2493 F03b
IM
FA
EN2
FB
SPD
Figure 3b. Timing Diagram for Writing to the LTC2493
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