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參數(shù)資料
| 型號： | LTC2494CUHF#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 15/38頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT W/PGA 38-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 38-QFN（5x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個(gè)單端，雙極；8 個(gè)差分，雙極 |
| 配用： | DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
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LTC2494
2494fd
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
Table 6. LTC2494 Interface Timing Modes
CONFIGURATION
SCK
SOURCE
CONVERSION
CYCLE CONTROL
DATA OUTPUT
CONTROL
CONNECTION AND
WAVEFORMS
External SCK, Single Cycle
Conversion
External
CS and SCK
Figures 6, 7
External SCK, 3-Wire I/O
External
SCK
Figure 8
Internal SCK, Single Cycle
Conversion
Internal
CS
↓
CS
↓
Figures 9, 10
Internal SCK, 3-Wire I/O,
Continuous Conversion
Internal
Continuous
Internal
Figure 11
SERIAL INTERFACE TIMING MODES
The LTC2494’s 4-wire interface is SPI and MICROWIRE
compatible. This interface offers several flexible modes
of operation. These include internal/external serial clock,
3-or4-wireI/O,singlecycleorcontinuousconversion.The
following sections describe each of these timing modes
in detail. In all cases, the converter can use the internal
oscillator (fO=LOW)oranexternaloscillatorconnectedto
the fO pin. For each mode, the operating cycle, data input
format, data output format and performance remain the
same. Refer to Table 6 for a summary.
External Serial Clock, Single Cycle Operation
This timing mode uses an external serial clock to shift out
the conversion result and CS to monitor and control the
state of the conversion cycle (see Figure 6).
Theexternalserialclockmodeisselectedduringthepower-
up sequence and on each falling edge of CS. In order to
enter and remain in the external SCK mode of operation,
SCK must be driven LOW both at power-up and on each
CS falling edge. If SCK is HIGH on the falling edge of CS,
the device will switch to the internal SCK mode.
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the conversion is complete and the device is in the sleep
state. Independent of CS, the device automatically enters
the sleep state once the conversion is complete; however,
in order to reduce the power, CS must be HIGH.
When the device is in the sleep state, its conversion result
isheldinaninternalstaticshiftregister.Thedeviceremains
in the sleep state until the first rising edge of SCK is seen
while CS is LOW. The input data is then shifted in via the
SDIpinoneachrisingedgeofSCK(includingthefirstrising
applications inForMation
TEMPERATURE (K)
0
DATAOUT
16
480
640
800
960
1020
400
2494 F04
320
0
300
200
100
160
VCC = 5V
VREF = 5V
SLOPE = 2.45 LSB16/K
TEMPERATURE (°C)
–55 –30
–5
ABSOLUTE
ERROR
(°C)
5
4
3
2
1
–4
–3
–2
–1
0
120
95
70
45
20
2494 F05
–5
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