參數(shù)資料
型號(hào): LTC2494IUHF#TRPBF
廠商: Linear Technology
文件頁(yè)數(shù): 20/38頁(yè)
文件大小: 0K
描述: IC ADC 16BIT W/PGA 38-QFN
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 16
采樣率(每秒): 15
數(shù)據(jù)接口: MICROWIRE?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 480µW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 38-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 16 個(gè)單端,雙極;8 個(gè)差分,雙極
配用: DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494
LTC2494
2494fd
remains unchanged. In order to program both the input
channel and converter configuration, CS must go HIGH
after the 16th falling edge of SCK (at this point all data
has been shifted into the device).
Internal Serial Clock, 3-Wire I/O, Continuous
Conversion.
This timing mode uses a 3-wire interface. The conversion
result is shifted out of the device by an internally generated
serial clock (SCK) signal (see Figure 11). In this case, CS is
permanently tied to ground, simplifying the user interface
or transmission over an isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 4ms after VCC exceeds 2V. An internal weak
pull-upisactiveduringthePORcycle;therefore,theinternal
serial clock timing mode is automatically selected if SCK
is floating or driven HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1). Once the conversion is
complete, SCK and SDO go LOW (EOC = 0) indicating
the conversion has finished and the device has entered
the sleep state. The device remains in the sleep state a
minimum amount of time (1/2 the internal SCK period)
then immediately begins outputting and inputting data.
The input data is shifted through the SDI pin on the ris-
ing edge of SCK (including the first rising edge) and the
output data is shifted out the SDO pin on the falling edge
of SCK. The data input/output cycle is concluded and a
new conversion automatically begins after the 24th rising
edge of SCK. During the next conversion, SCK and SDO
remain HIGH until the conversion is complete.
The Use of a 10k Pull-Up on SCK for Internal SCK
Selection
If CS is pulled HIGH while the converter is driving SCK
LOW, the internal pull-up is not available to restore SCK
to a logic HIGH state if SCK is floating. This will cause the
device to exit the internal SCK mode on the next falling
edge of CS. This can be avoided by adding an external 10k
pull-up resistor to the SCK pin.
applications inForMation
Figure 11. Internal Serial Clock, Continuous Operation
10F
0.1F
2.7V TO 5.5V
EOC
CS
SCK
(INTERNAL)
SDI
SDO
2494 F11
CONVERSION
DATA INPUT/OUTPUT
CONVERSION
BIT 20 BIT 19 BIT 18 BIT 17 BIT 16 BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 21
BIT 22
BIT 23
1
0
EN
SGL
A2
A1
A0
EN2
IM
FA
FB
SPD
GS2
GS1
GS0
ODD
BIT 10 BIT 9
BIT 0
2
3
1
4
5
6
7
8
9
10
11
12
13
14
15
16
24
DON'T CARE
MSB
SIG
“0”
VCC
fO
REF+
REF
CH0
CH7
CH8
CH15
COM
SCK
SDI
SDO
CS
GND
28
35
29
30
8
15
16
23
7
38
37
1,3,4,5,6,31,32,33,39
36
34
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUTS
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2494
3-WIRE
SPI INTERFACE
OPTIONAL
10k
VCC
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