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參數(shù)資料
| 型號： | LTC2495IUHF#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT W/PGA 38-QFN |
| 標準包裝： | 52 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 15 |
| 數(shù)據(jù)接口： | I²C，串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 480µW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 38-WFQFN 裸露焊盤 |
| 供應商設備封裝： | 38-QFN（5x7） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 16 個單端，雙極；8 個差分，雙極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 配用： | DC1012A-C-ND - BOARD DELTA SIGMA ADC LTC2495 |
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LTC2495
2495fd
I2C INTERFACE
The LTC2495 communicates through an I2C interface. The
I2C interface is a 2-wire, open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) LOW
and can never drive it HIGH. SDA is required to be exter-
nally connected to the supply through a pull-up resistor.
When the data line is not being driven, it is HIGH. Data on
the I2C bus can be transferred at rates up to 100kbits/s in
the standard mode and up to 400kbits/s in the fast mode.
The VCC power should not be removed from the device
when the I2C bus is active to avoid loading the I2C bus
lines through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
canalsobeconsideredasmastersorslaveswhenperform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2495 can only be addressed as a slave. Once
addressed, it can receive configuration bits (channel
selection, rejection mode, speed mode) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2495 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
The START and STOP Conditions
A START (S) condition is generated by transitioning SDA
from HIGH to LOW while SCL is HIGH. The bus is consid-
ered to be busy after the START condition. When the data
transfer is finished, a STOP (P) condition is generated by
transitioning SDA from LOW to HIGH while SCL is HIGH.
The bus is free after a STOP is generated. START and STOP
conditions are always generated by the master.
When the bus is in use, it stays busy if a repeated START
(Sr)isgeneratedinsteadofaSTOPcondition.Therepeated
START timing is functionally identical to the START and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the START condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
LOW or issue a Not Acknowledge (NACK) by leaving the
SDA line high impedance (the external pull-up resistor will
hold the line HIGH). Change of data only occurs while the
clock line (SCL) is LOW.
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
applications inForMation
SDA
SCL
S
Sr
P
S
tHD(SDA)
tHD(DAT)
tSU(STA)
tSU(STO)
tSU(DAT)
tLOW
tHD(SDA)
tSP
tBUF
tr
tf
tr
tf
tHIGH
2495 F02
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