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參數(shù)資料
| 型號： | LTC2600IGN |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP |
| 中文描述： | SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 428K |
| 代理商： | LTC2600IGN |
11
LTC2600/LTC2610/LTC2620
2600fa
Table 1.
COMMAND*
C3
C2
0
0
0
0
0
1
C1
0
0
1
1
0
1
C0
0
1
0
1
0
1
0
0
0
0
1
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
ADDRESS (n)*
A3
A2
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
A1
0
0
1
1
0
0
1
1
1
A0
0
1
0
1
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
All DACs
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2600, LTC2610 and LTC2620 respectively). Data can
only be transferred to the device when the CS/LD signal is
low.The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width,
8 don’t-care bits are transferred to the device first, fol-
lowed by the 24-bit word as just described. Figure 2b
OPERATIOU
Power-On Reset
The LTC2600/LTC2610/LTC2620 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2600/
2610/2620 contain circuitry to reduce the power-on glitch:
the analog outputs typically rise less than 10mV above
zero scale during power on if the power supply is ramped
to 5V in 1ms or more. In general, the glitch amplitude
decreases as the power supply ramp time is increased.
See Power-On Reset Glitch in the Typical Performance
Characteristics section.
Power Supply Sequencing
The voltage at REF (Pin 6) should be kept within the range
–0.3V
≤
V
REF
≤
V
CC
+ 0.3V (see Absolute Maximum
Ratings). Particular care should be taken to observe these
limits during power supply turn-on and turn-off sequences,
when the voltage at V
CC
(Pin 16) is in transition.
Transfer Function
The digital-to-analog transfer function is
k
OUT IDEAL
N
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and V
REF
is the voltage at REF
(Pin 6).
V
V
REF
(
)
=
*Command and address codes not shown are reserved and should not be used.
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