參數(shù)資料
型號(hào): LTC2604CGN
廠商: LINEAR TECHNOLOGY CORP
元件分類: DAC
英文描述: Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
中文描述: QUAD, SERIAL INPUT LOADING, 10 us SETTLING TIME, 16-BIT DAC, PDSO16
封裝: 0.150 INCH, PLASTIC, SSOP-16
文件頁(yè)數(shù): 10/16頁(yè)
文件大?。?/td> 389K
代理商: LTC2604CGN
10
LTC2604/LTC2614/LTC2624
2604f
Table 1.
COMMAND*
C3
C2
0
0
0
0
0
1
ADDRESS (n)*
A3
A2
0
0
0
0
0
0
0
0
1
1
C1
0
0
1
1
0
1
C0
0
1
0
1
0
1
0
0
0
0
1
1
Write to Input Register n
Update (Power Up) DAC Register n
Write to Input Register n, Update (Power Up) All n
Write to and Update (Power Up) n
Power Down n
No Operation
A1
0
0
1
1
1
A0
0
1
0
1
1
DAC A
DAC B
DAC C
DAC D
All DACs
OPERATIOU
Power-On Reset
The LTC2604/LTC2614/LTC2624 clear the outputs to zero
scale when power is first applied, making system initializa-
tion consistent and repeatable.
For some applications, downstream circuits are active
during DAC power-up, and may be sensitive to nonzero
outputs from the DAC during this time. The LTC2604/
LTC2614/LTC2624 contain circuitry to reduce the power-
on glitch; furthermore, the glitch amplitude can be made
arbitrarily small by reducing the ramp rate of the power
supply. For example, if the power supply is ramped to 5V
in 1ms, the analog outputs rise less than 10mV above
ground (typ) during power-on. See Power-On Reset Glitch
in the Typical Performance Characteristics section.
only be transferred to the device when the CS/LD signal is
low.The rising edge of CS/LD ends the data transfer and
causes the device to carry out the action specified in the
24-bit input word. The complete sequence is shown in
Figure 2a.
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads a 16-bit data word from the 32-bit shift register into
the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.
While the minimum input word is 24 bits, it may optionally
be extended to 32 bits. To use the 32-bit word width, 8
don’t-care bits are transferred to the device first, followed
by the 24-bit word as just described. Figure 2b shows the
32-bit sequence. The 32-bit word is required for daisy-
chain operation, and is also available to accommodate
microprocessors which have a minimum word width of 16
bits (2 bytes).
Power Supply Sequencing
The voltage at REF (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V
REF x
V
CC
+ 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at V
CC
(Pin 16) is in
transition.
Transfer Function
The digital-to-analog transfer function is
k
OUT IDEAL
N
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REF x is the voltage at REF A,
REF B, REF C and REF D (Pins 3, 6, 12 and 15).
V
REFx REFLO
[
REFLO
(
)
]
=
+
Serial Interface
The CS/LD input is level triggered. When this input is taken
low, it acts as a chip-select signal, powering-on the SDI
and SCK buffers and enabling the input shift register. Data
(SDI input) is transferred at the next 24 rising SCK edges.
The 4-bit command, C3-C0, is loaded first; then the 4-bit
DAC address, A3-A0; and finally the 16-bit data word. The
data word comprises the 16-, 14- or 12-bit input code,
ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits
(LTC2604, LTC2614 and LTC2624 respectively). Data can
*Command and address codes not shown are reserved and should not be used.
相關(guān)PDF資料
PDF描述
LTC2614 Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
LTC2604IGN Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
LTC2614IGN Quad 16-Bit Rail-to-Rail DACs in 16-Lead SSOP
LTC2605IGN-1 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP
LTC2605 Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP
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