參數資料
| 型號： | LTC2605IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數： | 14/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT OCT I2C 16-SSOP |
| 標準包裝： | 100 |
| 設置時間： | 10µs |
| 位數： | 16 |
| 數據接口： | I²C |
| 轉換器數目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
| 配用： | DC935A-ND - BOARD DAC LTC2605 |
LTC2605/LTC2615/LTC2625
5
2605fa
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. See Figure 1. (Notes 8, 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC = 2.7V to 5.5V
fSCL
SCL Clock Frequency
l
0
400
kHz
tHD(STA)
Hold Time (Repeated) Start Condition
l
0.6
μs
tLOW
Low Period of the SCL Clock Pin
l
1.3
μs
tHIGH
High Period of the SCL Clock Pin
l
0.6
μs
tSU(STA)
Set-Up Time for a Repeated Start Program
l
0.6
μs
tHD(DAT)
Data Hold Time
l
0
0.9
μs
tSU(DAT)
Data Set-Up Time
l
100
ns
tr
Rise Time of Both SDA and SCL Signals
(Note 7)
l 20 + 0.1CB
300
ns
tf
Fall Time of Both SDA and SCL Signals
(Note 7)
l 20 + 0.1CB
300
ns
tSU(STO)
Set-Up Time for Stop Condition
l
0.6
μs
tBUF
Bus Free Time Between a Stop and Start Condition
l
1.3
μs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are dened from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16,
kL = 256 and linearity is dened from code 256 to code 65,535.
Note 3: SDA, SCL at 0V or VCC, CA0, CA1 and CA2 oating.
Note 4: Inferred from measurement at code 256 (LTC2605/LTC2605-1),
code 64 (LTC2615/LTC2615-1) or code 16 (LTC2625/LTC2625-1) and at
full-scale.
Note 5: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale and
3/4-scale to 1/4-scale. Load is 2kΩ in parallel with 200pF to GND.
Note 6: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half-scale
and half-scale – 1. Load is 2kΩ in parallel with 200pF to GND.
Note 7: CB = capacitance of one bus line in pF.
Note 8: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 9: These specications apply to LTC2605/LTC2605-1,
LTC2615/LTC2615-1 and LTC2625/LTC2625-1.
Note 10: DC Crosstalk is measured with VCC = 5V and VREF = 4096V, with
the measured DAC at mid-scale, unless otherwise noted.
Note 11: RL = 2kΩ to GND or VCC.
Note 12: Guaranteed by design and not production tested.
ELECTRICAL CHARACTERISTICS
Test Circuit 1
Test Circuit 2
VIH(CA
n)
/VIL(CA
n)
CAn
100Ω
2605 TC01
GND
RINH/RINL/RINF
VDD
2605 TC02
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