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參數(shù)資料
| 型號： | LTC2606 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 16-/14-/12-Bit Rail-to-Rail DACs with I2C Interface |
| 中文描述： | 16/14/12軌到軌DAC的具有I2C接口 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 310K |
| 代理商： | LTC2606 |
10
LTC2606/LTC2616/LTC2626
26061626f
PI
FU
CTIO
N
S
U
U
CA2 (Pin 1):
Chip Address Bit 2. Tie this pin to V
CC
, GND
or leave it floating to select an I
2
C slave address for the part
(Table 1).
SDA (Pin 2):
Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
pin is high impedance while data is shifted in. Open drain
N-channel output during acknowledgment. SDA requires
a pull-up resistor or current source to V
CC
.
SCL (Pin 3):
Serial Clock Input Pin. Data is shifted into the
SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current source
to V
CC
.
CA0 (Pin 4):
Chip Address Bit 0. Tie this pin to V
CC
, GND
or leave it floating to select an I
2
C slave address for the part
(Table 1).
CA1 (Pin 5):
Chip Address Bit 1. Tie this pin to V
CC
, GND
or leave it floating to select an I
2
C slave address for the part
(Table 1).
REF (Pin 6):
Reference Voltage Input. 0V
≤
V
REF
≤
V
CC
.
V
OUT
(Pin 7):
DAC Analog Voltage Output. The output
range is 0V to V
REF
.
GND (Pin 8):
Analog Ground.
V
CC
(Pin 9):
Supply Voltage Input. 2.7V
≤
V
CC
≤
5.5V.
LDAC (Pin 10):
Asynchronous DAC Update. A falling edge
on this input after four bytes have been written into the part
immediately updates the DAC register with the contents of
the input register. A low on this input without a complete
32-bit (four bytes including the slave address) data write
transfer to the part does not update the DAC output.
Software power-down is disabled when LDAC is low.
Exposed Pad (Pin 11):
Ground. Must be soldered to PCB
ground.
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