ELECTRICAL CHARACTERISTICS The l
參數(shù)資料
型號： LTC2615IGN-1#PBF
廠商： Linear Technology
文件頁數(shù)： 13/18頁
文件大?。?/td> 0K
描述： IC DAC 14BIT R-R OCT 16SSOP
標(biāo)準(zhǔn)包裝： 100
設(shè)置時間： 9µs
位數(shù)： 14
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 8
電壓電源： 單電源
功率耗散（最大）： 6mW
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 管件
輸出數(shù)目和類型： 8 電壓，單極
采樣率（每秒）： *
LTC2605/LTC2615/LTC2625
4
2605fa
ELECTRICAL CHARACTERISTICS The l denotes the specications which apply over the full operating
temperature range, otherwise specications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded,
unless otherwise noted. (Note 9)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Digital I/O (Note 9)
VIL
Low Level Input Voltage (SDA and SCL)
l
0.3VCC
V
VIH
High Level Input Voltage (SDA and SCL)
l
0.7VCC
V
VIL(CA)
Low Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
0.15VCC
V
VIH(CA)
High Level Input Voltage (CA0 to CA2)
See Test Circuit 1
l
0.85VCC
V
RINH
Resistance from CAn (n = 0,1,2) to VCC
to Set CAn = VCC
See Test Circuit 2
l
10
kΩ
RINL
Resistance from CAn (n = 0,1,2) to GND
to Set CAn = GND
See Test Circuit 2
l
10
kΩ
RINF
Resistance from CAn (n = 0,1,2) to VCC
or GND to Set CAn = FLOAT
See Test Circuit 2
l
2MΩ
VOL
Low Level Output Voltage
Sink Current = 3mA
l
0
0.4
V
tOF
Output Fall Time
VO = VIH(MIN) to VO = VIL(MAX), CB = 10pF to 400pF
(Note 7)
l 20 + 0.1CB
250
ns
tSP
Pulse Width of Spikes Surpassed by
Input Filter
l
050
ns
IIN
Input Leakage
0.1VCC ≤ VIN ≤ 0.9VCC
l
1μA
CIN
I/O Pin Capacitance
(Note 12)
l
10
pF
CB
Capacitance Load for Each Bus Line
l
400
pF
CCAn
External Capacitive Load on Address
Pins CA0, CA1 and CA2
l
10
pF
The
l denotes the specications which apply over the full operating temperature range, otherwise specications are at TA = 25°C.
REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.7V), VOUT unloaded, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
LTC2625/LTC2625-1 LTC2615/LTC2615-1 LTC2605/LTC2605-1
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
AC Performance
tS
Settling Time (Note 5)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
77
9
7
9
10
μs
Settling Time for 1LSB Step
(Note 6)
±0.024% (±1LSB at 12 Bits)
±0.006% (±1LSB at 14 Bits)
±0.0015% (±1LSB at 16 Bits)
2.7
4.8
2.7
4.8
5.2
μs
Voltage Output Slew Rate
0.80
V/μs
Capacitive Load Driving
1000
pF
Glitch Inpulse
At Mid-Scale Transition
12
nVs
Multiplying Bandwidth
180
kHz
en
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
120
100
120
100
120
100
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz
15
μVP-P
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