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參數(shù)資料
| 型號： | LTC2620IUFD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 16/20頁 |
| 文件大小： | 0K |
| 描述： | IC DAC OCTAL R-R 12BIT 20-QFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 20mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 20-QFN 裸露焊盤（5x4） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
LTC2600/LTC2610/LTC2620
5
2600fe
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Linearity and monotonicity are dened from code kL to code
2N – 1, where N is the resolution and kL is given by kL = 0.016(2N/VREF),
rounded to the nearest whole code. For VREF = 4.096V and N = 16, kL =
256 and linearity is dened from code 256 to code 65,535.
Note 3: Digital inputs at 0V or VCC.
Note 4: DC crosstalk is measured with VCC = 5V and VREF = 4.096V,
with the measured DAC at mid-scale, unless otherwise noted.
Note 5: RL = 2kΩ to GND or VCC.
Note 6: Guaranteed by design and not production tested.
Note 7: Inferred from measurement at code 256 (LTC2600),
code 64 (LTC2610) or code 16 (LTC2620), and at full-scale.
Note 8: VCC = 5V, VREF = 4.096V. DAC is stepped 1/4-scale to 3/4-scale
and 3/4-scale to 1/4-scale. Load is 2k in parallel with 200pF to GND.
Note 9: VCC = 5V, VREF = 4.096V. DAC is stepped ±1LSB between half-
scale and half-scale – 1. Load is 2k in parallel with 200pF to GND.
TIMING CHARACTERISTICS The l denotes specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (See Figure 1) (Note 6)
SYMBOL PARAMETER
CONDITIONS
LTC2600/LTC2610/LTC2620
UNITS
MIN
TYP
MAX
VCC = 2.5V to 5.5V
t1
SDI Valid to SCK Setup
l
4ns
t2
SDI Valid to SCK Hold
l
4ns
t3
SCK High Time
l
9ns
t4
SCK Low Time
l
9ns
t5
CS/LD Pulse Width
l
10
ns
t6
LSB SCK High to CS/LD High
l
7ns
t7
CS/LD Low to SCK High
l
7ns
t8
SDO Propagation Delay from SCK Falling Edge
CLOAD = 10pF
VCC = 4.5V to 5.5V
VCC = 2.5V to 5.5V
l
20
45
ns
t9
CLR Pulse Width
l
20
ns
t10
CS/LD High to SCK Positive Edge
l
7ns
SCK Frequency
50% Duty Cycle
l
50
MHz
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