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參數(shù)資料
| 型號(hào)： | LTC2625CGN-1 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 317K |
| 代理商： | LTC2625CGN-1 |
3
LTC2605/LTC2615/LTC2625
2605f
SYMBOL
PSR
R
OUT
PARAMETER
Power Supply Rejection
DC Output Impedance
CONDITIONS
V
CC
±
10%
V
REF
= V
CC
= 5V, Midscale; –15mA
≤
I
OUT
≤
15mA
V
REF
= V
CC
= 2.7V, Midscale; –7.5mA
≤
I
OUT
≤
7.5mA
●
Due to Full Scale Output Change (Note 11)
Due to Load Current Change
Due to Powering Down (per Channel)
V
CC
= 5.5V, V
REF
= 5.5V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
V
CC
= 2.7V, V
REF
= 2.7V
Code: Zero Scale; Forcing Output to V
CC
Code: Full Scale; Forcing Output to GND
MIN
TYP
–80
0.02
0.03
±
10
±
3.5
±
7
MAX
UNITS
The
●
denotes specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25
°
C. REF = 4.096V (V
CC
= 5V), REF = 2.048V (V
CC
= 2.7V), V
OUT
unloaded,
unless otherwise noted. (Note 9)
ELECTRICAL C
HARA TERISTICS
dB
μ
V
●
0.15
0.15
DC Crosstalk (Note 10)
μ
V/mA
μ
V
I
SC
Short-Circuit Output Current
●
●
15
15
34
34
60
60
mA
mA
●
●
7.5
7.5
20
27
50
50
mA
mA
Reference Input
Input Voltage Range
Resistance
Capacitance
Reference Current, Power Down Mode
Power Supply
V
CC
Positive Supply Voltage
I
CC
Supply Current
●
0
V
CC
20
V
Normal Mode
●
11
16
90
k
pF
μ
A
I
REF
DAC Powered Down
●
0.001
1
For Specified Performance
V
CC
= 5V (Note 3)
V
CC
= 3V (Note 3)
DAC Powered Down (Note 3) V
CC
= 5V
DAC Powered Down (Note 3) V
CC
= 3V
●
2.7
5.5
4.0
3.2
1.0
1.0
V
●
●
●
●
2.50
2.00
0.38
0.16
mA
mA
μ
A
μ
A
Digital I/O (Note 9)
V
IL
Low Level Input Voltage
(SDA and SCL)
High Level Input Voltage
(SDA and SCL)
Low Level Input Voltage (CA0 to CA2)
High Level Input Voltage (CA0 to CA2)
Resistance from CA
n
(n = 0,1,2)
to V
CC
to Set CA
n
= V
CC
Resistance from CA
n
(n = 0,1,2)
to GND to Set CA
n
= GND
Resistance from CA
n
(n = 0,1,2)
to V
CC
or GND to Set CA
n
= FLOAT
Low Level Output Voltage
Output Fall Time
●
0.3V
CC
V
V
IH
●
0.7V
CC
V
V
IL(CA)
V
IH(CA)
R
INH
See Test Circuit 1
See Test Circuit 1
See Test Circuit 2
●
0.15V
CC
V
V
●
0.85V
CC
●
10
k
R
INL
See Test Circuit 2
●
10
k
R
INF
See Test Circuit 2
●
2
M
V
OL
t
OF
Sink Current = 3mA
V
O
= V
IH(MIN)
to V
O
= V
IL(MAX)
,
C
B
= 10pF to 400pF (Note 7)
●
0
0.4
250
V
●
20 + 0.1C
B
ns
t
SP
Pulse Width of Spikes Surpassed
by Input Filter
Input Leakage
I/O Pin Capacitance
Capacitance Load for Each Bus Line
External Capacitive Load on
Address Pins CA0, CA1 and CA2
●
0
50
ns
I
IN
C
IN
C
B
C
CAn
0.1V
CC
≤
V
IN
≤
0.9V
CC
(Note 12)
●
1
μ
A
pF
pF
pF
●
10
400
10
●
●
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