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參數(shù)資料
| 型號： | LTC2625IGN-1 |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | Octal 16-/14-/12-Bit Rail-to-Rail DACs in 16-Lead SSOP |
| 中文描述： | SERIAL INPUT LOADING, 7 us SETTLING TIME, 12-BIT DAC, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SSOP-16 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大小： | 317K |
| 代理商： | LTC2625IGN-1 |
12
LTC2605/LTC2615/LTC2625
2605f
The command (C3-C0) and address (A3-A0) assignments
are shown in Table 1. The first four commands in the table
consist of write and update operations. A write operation
loads the 16-bit data word from the 32-bit shift register
into the input register of the selected DAC, n. An update
operation copies the data word from the input register to
the DAC register. Once copied into the DAC register, the
data word becomes the active 16-, 14- or 12-bit input
code, and is converted to an analog voltage at the DAC
output. The update operation also powers up the selected
DAC if it had been in power-down mode. The data path and
registers are shown in the block diagram.
Table 2. Slave Address Map
CA2
CA1
GND
GND
GND
GND
GND
GND
GND
FLOAT
GND
FLOAT FLOAT
GND
FLOAT
GND
V
CC
GND
V
CC
GND
V
CC
FLOAT
GND
FLOAT
GND
FLOAT
GND
FLOAT FLOAT
FLOAT FLOAT FLOAT
FLOAT FLOAT
FLOAT
V
CC
FLOAT
V
CC
FLOAT
V
CC
V
CC
GND
V
CC
GND
V
CC
GND
V
CC
FLOAT
V
CC
FLOAT FLOAT
V
CC
FLOAT
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
GLOBAL ADDRESS
CA0
GND
FLOAT
V
CC
GND
SA6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SA5
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
SA4
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
SA3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SA2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
SA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
CC
GND
FLOAT
V
CC
GND
FLOAT
V
CC
GND
V
CC
GND
FLOAT
V
CC
GND
FLOAT
V
CC
GND
V
CC
GND
FLOAT
V
CC
Power Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever less
than eight outputs are needed. When in power-down, the
buffer amplifiers and reference inputs are disabled and
draw essentially zero current. The DAC outputs are put into
a high-impedance state, and the output pins are passively
pulled to ground through individual 90k resistors. When
all eight DACs are powered down, the bias generation
circuit is also disabled. Input- and DAC- registers are not
disturbed during power-down.
Any channel or combination of channels can be put into
power-down mode by using command 0100
b
in
combination with the appropriate DAC address, (n). The
16-bit data word is ignored. The supply and reference
currents are reduced by approximately 1/8 for each DAC
powered down; the effective resistance at REF (Pin 6) rises
accordingly, becoming a high-impedance input (typically
>1G
) when all eight DACs are powered down.
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 1.
The selected DAC is powered up as its voltage output
is updated.
There is an initial delay as the DAC powers up before it
begins its usual settling behavior. If less than eight DACs
are in a powered-down state prior to the updated
command, the power-up delay is 5
μ
s. If, on the other
hand, all eight DACs are powered down, then the bias
generation circuit is also disabled and must be restarted.
In this case, the power-up delay is greater: 12
μ
s for
V
CC
= 5V, 30
μ
s for V
CC
= 3V.
Voltage Outputs
Each of the eight rail-to-rail amplifiers contained in these
parts has guaranteed load regulation when sourcing or
sinking up to 15mA at 5V (7.5mA at 3V).
Load regulation is a measure of the amplifier’s ability
to maintain the rated voltage accuracy over a wide range
of load conditions. The measured change in output voltage
per milliampere of forced load current change is
expressed in LSB/mA.
OPERATIOU
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