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參數(shù)資料
| 型號： | LTC2625IGN#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R OCT 16SSOP |
| 標準包裝： | 2,500 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 8 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 6mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 8 電壓，單極 |
| 采樣率（每秒）： | * |
LTC2605/LTC2615/LTC2625
10
2605fa
PIN FUNCTIONS
BLOCK DIAGRAM
TIMING DIAGRAM
GND (Pin 1): Analog Ground.
VOUT A to VOUT H (Pins 2-5 and 12-15): DAC Analog Volt-
age Output. The output range is 0V to VREF.
REF (Pin 6): Reference Voltage Input. 0V ≤ VREF ≤ VCC.
CA2 (Pin 7): Chip Address Bit 2. Tie this pin to VCC, GND
or leave it oating to select an I2C slave address for the
part (Table 2).
SCL (Pin 8): Serial Clock Input Pin. Data is shifted into
the SDA pin at the rising edges of the clock. This high
impedance pin requires a pull-up resistor or current
source to VCC.
SDA (Pin 9): Serial Data Bidirectional Pin. Data is shifted
into the SDA pin and acknowledged by the SDA pin. This
is a high impedance pin while data is shifted in. It is an
open-drain N-channel output during acknowledgment. This
pin requires a pull-up resistor or current source to VCC.
CA1 (Pin 10): Chip Address Bit 1. Tie this pin to VCC, GND
or leave it oating to select an I2C slave address for the
part (Table 2).
CA0 (Pin 11): Chip Address Bit 0. Tie this pin to VCC, GND
or leave it oating to select an I2C slave address for the
part (Table 2).
VCC (Pin 16): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V.
2
15
1
GND
VOUT A
VOUT B
VOUT C
VOUT D
REF
CA2
SCL
VCC
VOUT H
VOUT G
VOUT F
VOUT E
CA0
CA1
SDA
2605 BD01
16
DAC A
3
14
4
13
5
7
6
8
10
11
9
12
2-WIRE INTERFACE
32-BIT SHIFT REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
DAC H
DAC B
DAC G
DAC C
DAC F
DAC D
DAC E
SDA
tf
S
tr
tLOW
tHD(STA)
ALL VOLTAGE LEVELS REFER TO VIH(MIN) AND VIL(MAX) LEVELS
tHD(DAT)
tSU(DAT)
tSU(STA)
tHD(STA)
tSU(STO)
tSP
tBUF
tr
tf
tHIGH
SCL
S
P
S
2605 F01
Figure 1
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