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參數(shù)資料
| 型號： | LTC2626IDD#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT I2C V-OUT 10-DFN |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 810µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸出數(shù)目和類型： | 1 電壓，單極 |
| 采樣率（每秒）： | * |
LTC2606/LTC2616/LTC2626
15
26061626fb
OPERATION
Power-Down Mode
For power-constrained applications, power-down mode
can be used to reduce the supply current whenever the
DAC output is not needed. When in power-down, the buffer
amplier, bias circuit and reference input is disabled and
draws essentially zero current. The DAC output is put into a
high impedance state, and the output pin is passively pulled
to ground through 90k resistors. Input- and DAC-register
contents are not disturbed during power-down.
Table 2
COMMAND*
C3
C2 C1 C0
0
Write to Input Register
0
1
Update (Power Up) DAC Register
0
1
Write to and Update (Power Up)
0
1
0
Power Down
1
No Operation
*Command codes not shown are reserved and should not be used.
The DAC channel can be put into power-down mode by
using command 0100b. The 16-bit data word is ignored.
The supply and reference currents are reduced to almost
zero when the DAC is powered down; the effective resis-
tance at REF becomes a high impedance input (typically
>1GΩ).
Normal operation can be resumed by executing any com-
mand which includes a DAC update, as shown in Table 2 or
performing an asychronous update (LDAC) as described
in the next section. The DAC is powered up as its voltage
output is updated. When the DAC in powered-down state
is powered up and updated, normal settling is delayed. The
main bias generation circuit block has been automatically
shut down in addition to the DAC amplier and reference
input and so the power-up delay time is:
12μs (for VCC = 5V) or 30μs (for VCC = 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2,
the LDAC pin asynchronously updates the DAC register
with the contents of the input register. Asynchronous
update is disabled when the input word is being clocked
into the part.
If a complete input word has been written to the part, a low
on the LDAC pin causes the DAC register to be updated
with the contents of the input register.
If the input word is being written to the part, a low going
pulse on the LDAC pin before the completion of three bytes
of data powers up the DAC but does not cause the output
to be updated. If LDAC remains low after a complete input
word has been written to the part, then LDAC is recognized,
the command specied in the 24-bit word just transferred
is executed and the DAC output is updated.
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2606)
Write Word Protocol for LTC2606/LTC2616/LTC1626
C2
C1
C0
X
D13
D14
D15
S
WA
SLAVE ADDRESS
1ST DATA BYTE
D12 D11 D10 D9
D8
D7 D6
D5
D4
D3
D2
D1 D0
A
2ND DATA BYTE
A
3RD DATA BYTE
A
P
2606 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2616)
C2
C1
C0
X
D11
D12
D13
D10 D9
D8
D7
D6
D5 D4
D3
D2
D1
D0
X
2ND DATA BYTE
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2626)
C2
C1
C0
X
D9
D10
D11
D8
D7
D6
D5
D4
D3 D2
D1
D0
X
2ND DATA BYTE
3RD DATA BYTE
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