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參數(shù)資料
| 型號(hào)： | LTC2627IDE-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R I2C 12-DFN |
| 標(biāo)準(zhǔn)包裝： | 91 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | I²C |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 780µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 12-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 12-DFN（4x3） |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1351 (CN2011-ZH PDF) |
LTC2607/LTC2617/LTC2627
26071727fa
operation
Table 2
COMMAND*
C3
C2
C1
C0
0
0 Write to Input Register
0
1 Update (Power Up) DAC Register
0
1
1 Write to and Update (Power Up)
0
1
0
0 Power Down
1
1 No Operation
ADDRESS*
A3
A2
A1
A0
0
0 DAC A
0
1 DAC B
1
1 All DACs
*Command and address codes not shown are reserved and should not be used.
Power-Down Mode
Forpower-constrainedapplications,thepower-downmode
can be used to reduce the supply current whenever one or
both of the DAC outputs are not needed. When in power-
down,thebufferamplifiers,biascircuitsandreferenceinput
are disabled and draw essentially zero current. The DAC
outputsareputintoahighimpedancestate,andtheoutput
pins are passively pulled to VREFLO through 90k resistors.
Input-registerandDAC-registercontentsarenotdisturbed
during power-down.
Either or both DAC channels can be put into power-down
mode by using command 0100b in combination with the
Figure 3
C3
1ST DATA BYTE
Input Word (LTC2607)
Write Word Protocol for LTC2607/LTC2617/LTC1627
C2 C1 C0 A3 A2 A1 A0
D13
D14
D15
S
W
A
SLAVE ADDRESS
1ST DATA BYTE
D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
A
2ND DATA BYTE
A 3RD DATA BYTE
A
P
2607 F03
2ND DATA BYTE
INPUT WORD
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2617)
C2 C1 C0 A3 A2 A1 A0
D11
D12
D13
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
2ND DATA BYTE
3RD DATA BYTE
C3
1ST DATA BYTE
Input Word (LTC2627)
C2 C1 C0 A3 A2 A1 A0
D9
D10
D11
D8 D7 D6 D5 D4 D3 D2 D1 D0
X
2ND DATA BYTE
3RD DATA BYTE
appropriate DAC address. The 16-bit data word is ignored.
The supply and reference currents are reduced by approxi-
mately 50% for each DAC powered down; the effective
resistance at REF (Pin 9) rises accordingly, becoming a
high-impedance input (typically > 1GΩ) when both DACs
are powered down.
Normal operation can be resumed by executing any
command which includes a DAC update, as shown in
Table 2 or performing an asychronous update (LDAC) as
describedinthenextsection.TheselectedDACispowered
upasitsvoltageoutputisupdated.WhenaDACinpowered-
down state is powered up and updated, normal settling
is delayed. If one of the two DACs is in a powered- down
state prior to the update command, the power up delay is
5s. If on the other hand, both DACs are powered down,
the main bias generation circuit has been automatically
shut down in addition to the DAC amplifiers and reference
input and so the power up delay time is
12s (for VCC = 5V) or 30s (for VCC = 3V)
Asynchronous DAC Update Using LDAC
In addition to the update commands shown in Table 2, the
LDAC pin asynchronously updates the DAC registers with
the contents of the input registers. Asynchronous update
is disabled when the input word is being clocked into
the part.
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