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參數(shù)資料
| 型號(hào)： | LTC2629CGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R QUAD 16SSOP |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 設(shè)置時(shí)間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 750µW |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1351 (CN2011-ZH PDF) |
LTC2609/LTC2619/LTC2629
26091929fb
operation
Power-On Reset
The LTC2609/LTC2619/LTC2629 clear the outputs to
zero-scale when power is first applied, making system
initialization consistent and repeatable. The LTC2609-1/
LTC2619-1/LTC2629-1setthevoltageoutputstomid-scale
when power is first applied.
Forsomeapplications,downstreamcircuitsareactivedur-
ingDACpower-upandmaybesensitivetononzerooutputs
from the DAC during this time. The LTC2609/LTC2619/
LTC2629 contain circuitry to reduce the power-on glitch;
furthermore, the glitch amplitude can be made arbitrarily
small by reducing the ramp rate of the power supply. For
example, if the power supply is ramped to 5V in 1ms, the
analog outputs rise less than 10mV above ground (typ)
during power-on. See Power-On Reset Glitch in the Typical
Performance Characteristics section.
Power Supply Sequencing
The voltage at REFx (Pins 3, 6, 12 and 15) should be kept
within the range –0.3V ≤ REFx ≤ VCC + 0.3V (see Absolute
Maximum Ratings). Particular care should be taken to
observe these limits during power supply turn-on and
turn-off sequences, when the voltage at VCC (Pin 16) is
in transition. The REFx pins can be clamped to stay below
the maximum voltage by using Schottky diodes as shown
in Figure 2, thereby easing sequencing constraints.
LTC2609/
LTC2619/
LTC2629
VCC
16
3
6
12
15
2609 F02
VCC
REFA
REFB
REFC
REFD
REFA
REFB
REFC
REFD
Figure 2. Use of Schottky Diodes for Power Supply Sequencing
Transfer Function
The digital-to-analog transfer function is:
V
k
REFx REFLO REFLO
OUT IDEAL
N
(
)
[
–
]
=
+
2
where k is the decimal equivalent of the binary DAC input
code, N is the resolution and REFx is the voltage at REFA,
REFB, REFC and REFD (Pins 3, 6, 12 and 15).
Serial Digital Interface
The LTC2609/LTC2619/LTC2629 communicate with a host
usingthestandard2-wireI2Cinterface.TheTimingDiagram
(Figure 1) shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines. The value of
thesepull-upresistorsisdependentonthepowersupplyand
can be obtained from the I2C specifications. For an I2C bus
operatinginthefastmode,anactivepull-upwillbenecessary
if the bus capacitance is greater than 200pF. The VCC power
shouldnotberemovedfromtheLTC2609/LTC2619/LTC2629
when the I2C bus is active to avoid loading the I2C bus lines
through the internal ESD protection diodes.
The LTC2609/LTC2619/LTC2629 are receive-only (slave)
devices. The master can write to the LTC2609/LTC2619/
LTC2629.TheLTC2609/LTC2619/LTC2629donotrespond
to a read from the master.
The START (S) and STOP (P) Conditions
Whenthebusisnotinuse,bothSCLandSDAmustbehigh.
A bus master signals the beginning of a communication
to a slave device by transmitting a START condition. A
START condition is generated by transitioning SDA from
high to low while SCL is high.
When the master has finished communicating with the
slave, it issues a STOP condition. A STOP condition is
generated by transitioning SDA from low to high while
SCL is high. The bus is then free for communication with
another I2C device.
Acknowledge
The Acknowledge signal is used for handshaking between
the master and the slave. An Acknowledge (active LOW)
generated by the slave lets the master know that the
latest byte of information was received. The Acknowledge
related clock pulse is generated by the master. The master
releasestheSDAline(HIGH)duringtheAcknowledgeclock
pulse. The slave-receiver must pull down the SDA bus line
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