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參數(shù)資料
| 型號： | LTC2629IGN#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT R-R QUAD 16SSOP |
| 標準包裝： | 100 |
| 設(shè)置時間： | 7µs |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 750µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極 |
| 采樣率（每秒）： | * |
| 產(chǎn)品目錄頁面： | 1351 (CN2011-ZH PDF) |
LTC2609/LTC2619/LTC2629
26091929fb
operation
main bias generation circuit block has been automatically
shut down in addition to the individual DAC amplifiers and
reference inputs. In this case, the power-up delay time is
12s (for VCC = 5V) or 30s (for VCC = 3V).
Voltage Output
The rail-to-rail amplifier has guaranteed load regulation
when sourcing or sinking up to 15mA at 5V (7.5mA at
2.7V).
Load regulation is a measure of the amplifier’s ability to
maintain the rated voltage accuracy over a wide range of
load conditions. The measured change in output voltage
permilliampereofforcedloadcurrentchangeisexpressed
in LSB/mA.
DC output impedance is equivalent to load regulation, and
may be derived from it by simply calculating a change in
units from LSB/mA to Ohms. The amplifier’s DC output
impedance is 0.035Ω when driving a load well away from
the rails.
When drawing a load current from either rail, the output
voltage headroom with respect to that rail is limited by
the 30Ω typical channel resistance of the output devices;
e.g., when sinking 1mA, the minimum output voltage =
30Ω 1mA = 30mV. See the graph Headroom at Rails vs
Output Current in the Typical Performance Characteristics
section.
The amplifier is stable driving capacitive loads of up to
1000pF.
Board Layout
TheexcellentloadregulationandDCcrosstalkperformance
of these devices is achieved in part by keeping “signal”
and “power” grounds separate.
The PC board should have separate areas for the analog
and digital sections of the circuit. This keeps digital signals
away from sensitive analog signals and facilitates the use
of separate digital and analog ground planes which have
minimal capacitive and resistive interaction with each
other.
Digital and analog ground planes should be joined at only
one point, establishing a system star ground as close to
the device’s ground pin as possible. Ideally, the analog
ground plane should be located on the component side of
the board, and should be allowed to run under the part to
shielditfromnoise.Analoggroundshouldbeacontinuous
and uninterrupted plane, except for necessary lead pads
and vias, with signal traces on another layer.
The GND pin functions as a return path for power supply
currents in the device and should be connected to analog
ground.ResistancefromtheGNDpintosystemstarground
should be as low as possible. When a zero-scale DAC
output voltage of zero is desired, REFLO (Pin 2) should
be connected to system star ground.
Rail-to-Rail Output Considerations
Inanyrail-to-railvoltageoutputdevice,theoutputislimited
to voltages within the supply range.
Since the analog output of the device cannot go below
ground, it may limit for the lowest codes as shown in
Figure4b.Similarly,limitingcanoccurnearfull-scalewhen
the REF pins are tied to VCC. If REFx = VCC and the DAC
full-scale error (FSE) is positive, the output for the highest
codes limits at VCC as shown in Figure 4c. No full-scale
limiting can occur if REFx is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
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