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參數(shù)資料
| 型號： | LTC263AHSC6-LZ12#TRMPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 4.4 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| 封裝： | LEAD FREE, PLASTIC, MO-203AB, SC-70, 6 PIN |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 341K |
| 代理商： | LTC263AHSC6-LZ12#TRMPBF |
LTC2630
12
2630f
BLOCK DIAGRAM
PIN FUNCTIONS
CS/LD (Pin 1): Serial Interface Chip Select/Load Input.
When
CS/LD is low, SCK is enabled for shifting data on
SDI into the register. When
CS/LD is taken high, SCK
is disabled and the specied command (see Table 1) is
executed.
SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL
compatible.
SDI (Pin 3): Serial Interface Data Input. Data on SDI
is clocked into the DAC on the rising edge of SCK. The
LTC2630 accepts input word lengths of either 24 or 32
bits.
VCC (Pin 4): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V
(LTC2630-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2630-H). Also
used as the reference input when the part is programmed
to operate in supply as reference mode. Bypass to GND
with a 0.1
μF capacitor.
GND (Pin 5): Ground.
VOUT (Pin 6): DAC Analog Voltage Output.
DAC
REGISTER
RESISTOR
DIVIDER
INTERNAL
REFERENCE
INPUT
REGISTER
24-BIT
SHIFT
REGISTER
DAC
VOUT
CONTROL
DECODE LOGIC
CS/LD
VCC
GND
DACREF
2630 BD
SCK
SDI
相關(guān)PDF資料 |
PDF描述 |
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| LTC263AISC6-HM12#TRMPBF | SERIAL INPUT LOADING, 4.8 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| LTC263AISC6-HZ12#TRPBF | SERIAL INPUT LOADING, 4.8 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| LTC263AISC6-LM12#TRMPBF | SERIAL INPUT LOADING, 4.4 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| LTC263AISC6-LM12#TRPBF | SERIAL INPUT LOADING, 4.4 us SETTLING TIME, 12-BIT DAC, PDSO6 |
| LTC263AISC6-HM12#TRPBF | SERIAL INPUT LOADING, 4.8 us SETTLING TIME, 12-BIT DAC, PDSO6 |
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