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參數(shù)資料
| 型號： | LTC2704IGW-14#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 8/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 14BIT QUAD VOUT 44-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | LTC275x 18-Bit DAC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 設(shè)置時間： | 9µs |
| 位數(shù)： | 14 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 44-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 4 電壓，單極；4 電壓，雙極 |
| 采樣率（每秒）： | * |
LTC2704
16
2704fd
should be driven with a Thevenin-equivalent impedance
of 10kΩ or less. If not used, they should be shorted to
their respective signal grounds, AGNDx.
POWER-ON RESET AND CLEAR
When power is rst applied to the LTC2704, all DACs
power-up in 5V unipolar mode (S3 S2 S1 S0 = 0000). All
internal DAC registers are reset to 0 and the DAC outputs
are zero volts.
When the CLR pin is taken low, a system clear results. The
command and address shift registers, and the code and
conguration B2 buffers, are reset to 0; the DAC outputs
are all reset to zero volts. The B1 buffers are left intact, so
that any subsequent “Update B1→B2” command (includ-
ing the use of LDAC) restores the addressed DACs to their
respective previous states.
If CLR is asserted during an operation, i.e., when CS/LD
is low, the operation is aborted. Integrity of the relevant
input (B1) buffers is not guaranteed under these condi-
tions, therefore the contents should be checked using
readback or replaced.
The RFLAG pin is used as a ag to notify the system of a
loss of data integrity. The RFLAG output is asserted low
at power-up, system clear, or if the logic supply VDD dips
below approximately 2V; and stays asserted until any valid
update command is executed.
SLEEP MODE
When a sleep command (C3 C2 C1 C0 = 1110) is issued,
the addressed DAC or DACs go into power-down mode.
DACs A and B share a reference inverting amplier as do
DACs C and D. If either DAC A or DAC B (similarly for DACs
C and D) is powered down, its shared reference inverting
amplier remains powered on. When both DAC A and DAC B
are powered down together, their shared reference invert-
ing amplier is also powered down (similarly for DACs C
and D). To determine the sleep status of a particular DAC,
a direct read span command is performed by addressing
the DAC and reading its status on the readback pin SRO.
The fth LSB is the sleep status bit (see Figures 2a and
2b). Table 4 shows the sleep status bit’s functionality.
Table 4. Readback Sleep Status Bit
SLP
STATUS
0
DAC n Awake
1
DAC n in Sleep Mode
OPERATION
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| LTC2704IGW-16#PBF | 功能描述:IC DAC 16BIT QUAD VOUT 44-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
| LTC2704IGW-16#TRPBF | 功能描述:IC DAC 16BIT QUAD VOUT 44-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| LTC2713CM-G | 制造商:Lite-On Semiconductor Corporation 功能描述: |
| LTC-2721B | 功能描述:LED 顯示器和配件 Blue 3 Dig 0.28" Ht 466nm 3000ucd RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
| LTC-2721E | 功能描述:LED 顯示器和配件 3 Digit, Orange RoHS:否 制造商:Avago Technologies 顯示器類型:7 Segment 數(shù)位數(shù)量:2 字符大小:7.8 mm x 14.22 mm 照明顏色:Red 波長:628 nm 共用管腳:Common Anode 工作電壓:2.05 V 工作電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 35 C 封裝:Tube |
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