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參數(shù)資料
| 型號： | LTC2752AILX#PBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | DAC |
| 英文描述： | 16-BIT DAC, PQFP48 |
| 封裝： | 7 X 7 MM, LEAD FREE, PLASTIC, MS-026, LQFP-48 |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 360K |
| 代理商： | LTC2752AILX#PBF |
LTC2752
2752f
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t8
CS/LD High to SCK Positive Edge
l
5
ns
t9
SRO Propagation Delay
CLOAD = 10pF
l
26
ns
t10
CLR Pulse Width Low
l
60
ns
t11
LDAC Pulse Width Low
l
20
ns
t12
CLR Low to RFLAG Low
CLOAD = 10pF (Note 13)
l
70
ns
t13
CS/LD High to RFLAG high
CLOAD = 10pF (Note 13)
l
60
ns
SCK Frequency
50% Duty Cycle (Note 14)
l
25
MHz
TiMing characTerisTics The
l
denotes specifications that apply over the full operating temperature range,
otherwise specifications are at TA = 25°C.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and IOUT1 leakage current
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from RINX to RCOMX; feedback resistors
measured from RCOMX to REFX.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
IOUT1X and from the specified pin to IOUT2X.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9. Full-scale transition; REF = 0V.
Note 10. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave.
Note 11. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 12. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and
B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale.
Note 13. Guaranteed by design, not subject to test.
Note 14. When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
f
t
MAX
S
=
+
(
)
1
2 9
, where tS is the setup time of the receiving device.
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